[Release/3.2.x] AMD Cherry Picks #5413
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Cherry pick list: - triton-lang#4925 - triton-lang#5053 - triton-lang#5019 - triton-lang#5002 - triton-lang#4935 - required additional cherry picks triton-lang#4991 and triton-lang#4951 - triton-lang#4998 - triton-lang#4925 - triton-lang#5281 - triton-lang#5308 - All previous LLVM hash PRs before triton-lang#5308 --------- Co-authored-by: Ilya V <[email protected]> Co-authored-by: Lei Zhang <[email protected]> Co-authored-by: Lixun Zhang <[email protected]> Co-authored-by: Keren Zhou <[email protected]> Co-authored-by: Alexander Efimov <[email protected]> Co-authored-by: Kyle Wang <[email protected]> Co-authored-by: Jungwook Park <[email protected]> Co-authored-by: peterbell10 <[email protected]> Co-authored-by: Hongtao Yu <[email protected]>
Reverts triton-lang#5191 due to some mlir errors in pytorch unit tests Smaller set of cherry picks: - triton-lang#5308 (and previous LLVM upgrades) - triton-lang#5281 - triton-lang#4925 - triton-lang#5053 - triton-lang#5019 - triton-lang#4998 --------- Co-authored-by: Jungwook Park <[email protected]> Co-authored-by: peterbell10 <[email protected]> Co-authored-by: Hongtao Yu <[email protected]> Co-authored-by: Lei Zhang <[email protected]> Co-authored-by: Ilya V <[email protected]> Co-authored-by: Kyle Wang <[email protected]>
This reverts commit 7e401df.
This reverts commit 2d8093c.
In the case of 16 bit floats operands for tt::AtomicRMWOp, construct only one LLVM::AtomicRMWOp but use vector of elements. Such approach allows to generate packed intrinsics and process 2 elements at once. Added a lit test for f16 vectorized case. (cherry picked from commit 78c8054)
(cherry picked from commit 86a2ac7)
This commit adds support for warp-level reduction with DPP instructions, which can improve performance. See https://gpuopen.com/learn/amd-gcn-assembly-cross-lane-operations/ (cherry picked from commit 21119e3)
TritonAMDGPUTransforms now depends on it. (cherry picked from commit 0b443ce)
This relands triton-lang#5392 to enable new arch target since backend support has been added--it doesn't depend on the reverted LLVM upgrade in triton-lang#5341; basic necessary enablement is already included in the current llvm version we're using. (cherry picked from commit f257479)
Fixes triton-lang#4769 (cherry picked from commit f484cb8)
triton-lang#5064) Bumping llvm to include a loop unroller fix: llvm/llvm-project#114573. This is needed for subsequent loop unroller upstreaming work. (cherry picked from commit 3c296ab)
This pulls in llvm/llvm-project@bd9145c8c213 to enable ASan on AMD backend. (cherry picked from commit 0bd30a2)
This includes llvm/llvm-project#115627 (cherry picked from commit 6404fbb)
jataylo
requested review from
antiagainst,
ptillet and
zhanglx13
as code owners
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antiagainst
approved these changes
Dec 12, 2024
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@jataylo this is a lot of feature work, not landed yet on pytorch/main. Normally after branch cut we accept only critical fixes. cc @malfet @bertmaher |
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Testing performed at: pytorch/pytorch#142240
This PR brings in several cherry picks from upstream triton for AMD backend and LLVM bumps. This is primarily for AMD optimisation and new architecture support from the LLVM bump.