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[BACKEND] Bump to llvm/llvm-project@1188b1ff7b95 #5884

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Merged
merged 5 commits into from
Feb 12, 2025
Merged

[BACKEND] Bump to llvm/llvm-project@1188b1ff7b95 #5884

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1a120b3
[BACKEND]Bump llvm to 1188b1ff
yiqian1 Feb 11, 2025
0cc7235
Merge branch 'main' into bump-llvm
antiagainst Feb 12, 2025
4469740
Catch up to CallOp llvm changes
yiqian1 Feb 12, 2025
be9f128
Merge branch 'main' into bump-llvm
yiqian1 Feb 12, 2025
a4db030
Catch up to rocdl waitcntOp change
yiqian1 Feb 12, 2025
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2 changes: 1 addition & 1 deletion cmake/llvm-hash.txt
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
ffe3129e9bdc146ee4d91e849173d1c64b1ae974
1188b1ff7b956cb65d8ddda5f1e56c432f1a57c7
5 changes: 4 additions & 1 deletion include/triton/Dialect/Triton/IR/TritonOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1055,7 +1055,10 @@ def CallOp : TT_Op<"call", [CallOpInterface, /*MemRefsNormalizable, */DeclareOpI
```
}];

let arguments = (ins FlatSymbolRefAttr:$callee, Variadic<AnyType>:$operands);
let arguments = (ins FlatSymbolRefAttr:$callee,
Variadic<AnyType>:$operands,
OptionalAttr<DictArrayAttr>:$arg_attrs,
OptionalAttr<DictArrayAttr>:$res_attrs);
let results = (outs Variadic<AnyType>);

let builders = [
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2 changes: 1 addition & 1 deletion lib/Dialect/Triton/IR/Ops.cpp
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Expand Up @@ -922,7 +922,7 @@ void FuncOp::build(OpBuilder &builder, OperationState &state, StringRef name,
if (argAttrs.empty())
return;
assert(type.getNumInputs() == argAttrs.size());
function_interface_impl::addArgAndResultAttrs(
call_interface_impl::addArgAndResultAttrs(
builder, state, argAttrs, /*resultAttrs=*/std::nullopt,
getArgAttrsAttrName(state.name), getResAttrsAttrName(state.name));
}
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8 changes: 4 additions & 4 deletions test/Conversion/amd/async_ops_to_llvm.mlir
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Expand Up @@ -83,16 +83,16 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.shar
%arg1: i32 {tt.divisibility = 16 : i32},
%arg2: !ttg.memdesc<32x64xf16, #shared, #smem, mutable>) {
// The waitcnt stores all counters in one i32 bits 15:14 and 3:0 store the vmcnt we have to wait on
// CHECK: rocdl.waitcnt -49168
// CHECK: rocdl.s.waitcnt -49168
// CHECK: rocdl.barrier
ttg.async_wait {num = 0 : i32}
// CHECK: rocdl.waitcnt -49167
// CHECK: rocdl.s.waitcnt -49167
// CHECK: rocdl.barrier
ttg.async_wait {num = 1 : i32}
// CHECK: rocdl.waitcnt -2
// CHECK: rocdl.s.waitcnt -2
// CHECK: rocdl.barrier
ttg.async_wait {num = 62 : i32}
// CHECK: rocdl.waitcnt -1
// CHECK: rocdl.s.waitcnt -1
// CHECK: rocdl.barrier
ttg.async_wait {num = 63 : i32}
tt.return
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2 changes: 1 addition & 1 deletion third_party/amd/lib/TritonAMDGPUToLLVM/LoadStoreOpToLLVM.cpp
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Expand Up @@ -1682,7 +1682,7 @@ struct AsyncWaitOpConversion : public ConvertOpToLLVMPattern<AsyncWaitOp> {
unsigned otherCnts = ~0xC00F; // C00F has bits 15:14 and 3:0 set
unsigned waitValue = lowBits | highBits | otherCnts;

rewriter.create<ROCDL::WaitcntOp>(loc, waitValue);
rewriter.create<ROCDL::SWaitcntOp>(loc, waitValue);

// Drop the result AsyncToken
rewriter.replaceOp(op, b.i32_val(0));
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