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[NVIDIA] Replace some NVGPU ops with equivalent NVVM ops (part 2) #7471

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Merged
merged 4 commits into from
Jul 14, 2025
Merged

[NVIDIA] Replace some NVGPU ops with equivalent NVVM ops (part 2) #7471

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b840317
Replace FenceAsyncSharedOp
Pecco-314 Jul 11, 2025
e408e1a
Add ConvertNVVMToLLVMPass to the pipeline
Pecco-314 Jul 11, 2025
838195c
Replace LoadMatrixOp and StoreMatrixOp
Pecco-314 Jul 11, 2025
be2ce55
Update the test
Pecco-314 Jul 11, 2025
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6 changes: 4 additions & 2 deletions python/test/unit/language/test_tensor_descriptor.py
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Original file line number Diff line number Diff line change
Expand Up @@ -609,7 +609,8 @@ def alloc_fn(size: int, align: int, stream: Optional[int]):
if BLOCK_M >= 64 * num_ctas and BLOCK_N >= 64 and is_hopper():
# TODO: The use of stmatrix for Blackwell is currently not supported.
# Only a subset of TMEM and stmatrix layout pairs are compatible, for example 16x256bx2 and m8n8x4.
assert "stmatrix.sync.aligned.m8n8.x4.shared.b16" in kernel.asm["ptx"]
assert "stmatrix.sync.aligned.m8n8.x4.shared.b16" in kernel.asm[
"ptx"] or "stmatrix.sync.aligned.x4.m8n8.shared.b16" in kernel.asm["ptx"]


@triton.jit
Expand Down Expand Up @@ -1668,4 +1669,5 @@ def test_host_tensor_descriptor_matmul(num_stages, num_ctas, BLOCK_M, BLOCK_N, B
if BLOCK_M >= 64 * num_ctas and BLOCK_N >= 64 and is_cuda() and is_hopper():
# TODO: The use of stmatrix for Blackwell is currently not supported.
# Only a subset of TMEM and stmatrix layout pairs are compatible, for example 16x256bx2 and m8n8x4.
assert "stmatrix.sync.aligned.m8n8.x4.shared.b16" in kernel.asm["ptx"]
assert "stmatrix.sync.aligned.m8n8.x4.shared.b16" in kernel.asm[
"ptx"] or "stmatrix.sync.aligned.x4.m8n8.shared.b16" in kernel.asm["ptx"]
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