TROPIC01 RTL

This repository is TROPIC01 RTL (Register Transfer level) HW design source code. The RTL is written in System Verilog, and it contains the auditable part of TROPIC01 secure element chip.

The repository contains a simple testbench to demnostrate functionality of TROPIC01 design.

Dependencies

To run simulations in this repository, you will need:

• verilator - To simulate, tested with version 5.034
• gtkwave - To view waves, tested with version 3.3.124

How to run simulation

Clean previous build with:

make clean

Run simulation of a test with:

make test TEST_NAME=<name of the test>

List of test examples

Name	Description
basic_test	Power-up the chip and wait until it enters Virgin state
block_id_test	Read BLOCK_ID of each HW block via test interface

after running the simulations, you can view waves by:

gtkwave tassic_tb_top.fst

Performance

Note that despite Verilator being a fast simulator, compilation and elaboration of TROPIC01 design takes long time (around 9 minutes on 20-core Intel Core i9 12900h).

Design Data

Since parts of the TROPIC01 design is proprietary, this repository includes behavioral mock-ups for following blocks:

• Bedrock (Power management, TRNG, PUF, Oscillator, Sensors)
• OTP Memory (I-Memory)

Flash Memory controller and Flash Memory (R-Memory) was replaced by an empty box since these blocks are tightly coupled to third-party intellectual property.

The RISCV CPU ROM memory does contain only empty memory. In TROPIC01 chips, it contains a Bootloader. Bootloader is not published yet, therefore this HEX file is ommitted.

Further, few small modifications were necessary to make the design compilable in Verilator:

• IO pads were split to "In" and "Out" since Verilator can't handle HiZ
• In-design functional cover points were removed since Verilator does not support them.
• Couple of other minor tweaks.

Other than these changes, the RTL corresponds to TROPIC01 sold with Part Number prefix: TR01-CXX-XXXX.

Documentation

• doc/chip_top - TROPIC01 HW functional specification
• doc/subsystems - Specifications of individual IP cores
• doc/theory - For theoretical work behind TROPIC01

Note that the published TROPIC01 hardware documentation has been modified to remove any third-party proprietary or technology-specific information.

Verification

The tassic_tb_top testbench in this repository is only demonstrative.

TROPIC01 design was verified internally. Each IP block has a UVM testbench that is integrated into chip-top UVM testbench. These test-benches are not published since Verilator can't handle them at the time of publishing.

See doc/subsystems/testplans for verification plans of Tropic Square internal testbench.

See test_results folder for test results and mapping between tests and verification items.

Contributions

This repository does not accept external contributions. It provides a snapshop of TROPIC01 design to support auditability.

If you are interested in contributing to Tropic Square's product development, please reach out to us via company or support contacts.