TAPA

TAPA is a powerful framework for designing high-frequency FPGA dataflow accelerators. It provides a powerful C++ API for expressing task-parallel designs with advanced optimization techniques to deliver exceptional design performance and productivity.

TAPA is community maintained by Tsinghua University TUNA Association.

• High-Frequency Performance: Achieve 2x higher frequency on average compared to Vivado¹.
• Rapid Development: 7x faster compilation and 3x faster software simulation than Vitis HLS².
• Expressive API: Rich C++ syntax with dedicated APIs for complex memory access patterns and explicit parallelism.
• HBM Optimizations: Automated design space exploration and physical optimizations for HBM FPGAs.

Quick Start

Installing from Releases

The easiest way to install TAPA is from a pre-built release:

curl -fsSL https://raw.githubusercontent.com/tuna/tapa/main/install.sh | sh -s -- -q

This downloads and installs the latest release. With root privileges, TAPA installs to /opt/tapa with symlinks in /usr/local/bin. Otherwise it installs to ~/.tapa and adds it to your PATH via your shell profile.

To install a specific version:

TAPA_VERSION=0.1.20260319 \
  curl -fsSL https://raw.githubusercontent.com/tuna/tapa/main/install.sh | sh -s -- -q

Releases are available at github.com/tuna/tapa/releases.

Prerequisites

• Ubuntu 18.04+, Debian 10+, RHEL 9+, Fedora 34+, or Amazon Linux 2023
• Vitis HLS 2022.1 or later

Building from Source

# Install dependencies (Ubuntu/Debian example)
sudo apt-get install g++ binutils git python3

# Install Bazel (see https://bazel.build/install)

# Clone the repository
git clone https://github.com/tuna/tapa.git
cd tapa

# Build TAPA
bazel build //...

# Build without tests
bazel build //... -- -//tests/...

See the Building from Source guide for detailed instructions.

Compilation

cd tests/apps/vadd

# Software simulation (use bazel-bin/tapa/tapa if built from source)
tapa g++ vadd.cpp vadd-host.cpp -o vadd
./vadd

# Hardware compilation and emulation
tapa compile \
   --top VecAdd \
   --part-num xcu250-figd2104-2L-e \
   --clock-period 3.33 \
   -f vadd.cpp \
   -o vecadd.xo
./vadd --bitstream=vecadd.xo 1000

Visualization

TAPA includes a web-based visualizer in the tapa-visualizer/ directory. You can build and run it locally to visualize your design's graph.json file generated during compilation.

For detailed instructions, see our User Guide.

Documentation

• Quick Reference.
• User Guide.
• Installation Guide.
• Getting Started.
• API Reference.

Success Stories

• Serpens (DAC'22): 270 MHz on Xilinx Alveo U280 HBM board with 24 HBM channels, while the Vitis HLS baseline failed in routing.
• Sextans (FPGA'22): 260 MHz on Xilinx Alveo U250 board with 4 DDR channels, while the Vivado baseline achieves only 189 MHz.
• SPLAG (FPGA'22): Up to 4.9x speedup over state-of-the-art FPGA accelerators, up to 2.6x speedup over 32-thread CPU running at 4.4 GHz, and up to 0.9x speedup over an A100 GPU.
• AutoSA Systolic-Array Compiler (FPGA'21): Significant frequency improvements over the Vitis HLS baseline.
• KNN (FPT'20): 252 MHz on Xilinx Alveo U280 board, compared to 165 MHz with the Vivado baseline.

Licensing

TAPA is open-source software licensed under the MIT license. For full license details, please refer to the LICENSE file.

Publications

1. Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs. FPGA, 2021. (Best Paper Award)
2. Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong. Extending high-level synthesis for task-Parallel programs. FCCM, 2021.
3. Young-kyu Choi, Yuze Chi, Jason Lau, Jason Cong. TARO: Automatic optimization for free-running kernels in FPGA high-level synthesis. TCAD, 2022.
4. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong. RapidStream 2.0: Automated parallel implementation of latency insensitive FPGA designs through partial reconfiguration. TRETS, 2023.
5. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong. TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design. TRETS, 2023.

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Copyright (c) 2026 TAPA community maintainers and contributors.
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.
Copyright (c) 2020 Yuze Chi and contributors.