Pipeline the FP divider and sqrt paths in fp_div_shim

  Convert fp_divider.sv and fp_sqrt.sv from sequential FSMs to fully
  pipelined datapaths using generate blocks to unroll the iterative
  division/sqrt loops. Pipeline depths: SP=36 stages, DP=65 stages.

  Rewrite fp_div_shim to directly instantiate 4 sub-units (div_s, div_d,
  sqrt_s, sqrt_d) with per-sub-unit tag queue shift registers, holding
  registers, a fixed-priority arbiter, and a depth-4 result FIFO.
  Credit-based back-pressure prevents FIFO overflow. Add i_div_accepted
  port and wire fp_div_result_accepted in tomasulo_wrapper.

  Retain o_stall port (tied low) on both pipelined units for backward
  compatibility with the in-order fpu_div_sqrt_unit, which connects but
  does not read it.

  Update cocotb tests with FIFO-based output protocol (drive i_div_accepted
  to pop results) and add pipeline-specific tests: back-to-back issue,
  interleaved div/sqrt, multi-op flush, and FIFO backpressure.

Author: adambagley

README.md

@@ -303,16 +303,16 @@ Running `pytest tests/` exercises:
 
 | Resource | Used | Available | Util% |
 |----------|-----:|----------:|------:|
-| CLB LUTs | 30,686 | 1,029,600 | 3.0% |
-|   LUT as Logic | 29,425 | 1,029,600 | 2.9% |
+| CLB LUTs | 48,040 | 1,029,600 | 4.7% |
+|   LUT as Logic | 46,481 | 1,029,600 | 4.5% |
 |   LUT as Distributed RAM | 1,168 | — | — |
-|   LUT as Shift Register | 93 | — | — |
-| CLB Registers | 19,936 | 2,059,200 | 1.0% |
+|   LUT as Shift Register | 391 | — | — |
+| CLB Registers | 37,747 | 2,059,200 | 1.8% |
 | Block RAM Tile | 68.5 | 2,112 | 3.2% |
 | URAM | 0 | 352 | 0.0% |
 | DSPs | 30 | 1,320 | 2.3% |
-| CARRY8 | 765 | 128,700 | 0.6% |
-| F7 Muxes | 384 | 514,800 | 0.1% |
+| CARRY8 | 2,790 | 128,700 | 2.2% |
+| F7 Muxes | 385 | 514,800 | 0.1% |
 | F8 Muxes | 2 | 257,400 | 0.0% |
 | Bonded IOB | 4 | 364 | 1.1% |
 | MMCM | 1 | 11 | 9.1% |
@@ -322,14 +322,14 @@ Running `pytest tests/` exercises:
 
 | Resource | Used | Available | Util% |
 |----------|-----:|----------:|------:|
-| Slice LUTs | 29,843 | 203,800 | 14.6% |
-|   LUT as Logic | 28,446 | 203,800 | 14.0% |
+| Slice LUTs | 46,683 | 203,800 | 22.9% |
+|   LUT as Logic | 44,988 | 203,800 | 22.1% |
 |   LUT as Distributed RAM | 1,308 | — | — |
-|   LUT as Shift Register | 89 | — | — |
-| Slice Registers | 19,431 | 407,600 | 4.8% |
+|   LUT as Shift Register | 387 | — | — |
+| Slice Registers | 37,151 | 407,600 | 9.1% |
 | Block RAM Tile | 68.5 | 445 | 15.4% |
 | DSPs | 34 | 840 | 4.0% |
-| F7 Muxes | 316 | 101,900 | 0.3% |
+| F7 Muxes | 386 | 101,900 | 0.4% |
 | F8 Muxes | 2 | 50,950 | 0.0% |
 | Bonded IOB | 6 | 500 | 1.2% |
 | MMCM | 1 | 10 | 10.0% |
@@ -339,14 +339,14 @@ Running `pytest tests/` exercises:
 
 | Resource | Used | Available | Util% |
 |----------|-----:|----------:|------:|
-| Slice LUTs | 29,630 | 63,400 | 46.7% |
-|   LUT as Logic | 28,233 | 63,400 | 44.5% |
+| Slice LUTs | 46,683 | 63,400 | 73.6% |
+|   LUT as Logic | 44,988 | 63,400 | 71.0% |
 |   LUT as Distributed RAM | 1,308 | — | — |
-|   LUT as Shift Register | 89 | — | — |
-| Slice Registers | 19,463 | 126,800 | 15.3% |
+|   LUT as Shift Register | 387 | — | — |
+| Slice Registers | 37,151 | 126,800 | 29.3% |
 | Block RAM Tile | 68.5 | 135 | 50.7% |
 | DSPs | 34 | 240 | 14.2% |
-| F7 Muxes | 374 | 31,700 | 1.2% |
+| F7 Muxes | 384 | 31,700 | 1.2% |
 | F8 Muxes | 2 | 15,850 | 0.0% |
 | Bonded IOB | 4 | 210 | 1.9% |
 | MMCM | 1 | 6 | 16.7% |