cpu: riscv: softmax: add f16 support #4491
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zhangjian29
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Co-authored-by: Fei Zhang <zhangfei@iscas.ac.cn>
Co-authored-by: Fei Zhang <zhangfei@iscas.ac.cn>
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Description
This PR adds support for FP16 (half-precision) data type to the RISC-V Vector (RVV) Softmax primitive.
Added compute_softmax_f16_rvv which utilizes Zvfh intrinsics. To ensure precision, the kernel performs accumulation and exponential/logarithm calculations in f32 (using widening conversions __riscv_vfwcvt) and converts back to f16 for the final output.
Checklist
General
make testandmake test_benchdnn_*) pass locally for each commit?Performance improvements
Performance was evaluated on SG2044 (RISC-V) using 16 cores (pinned). The comparison is between the new RVV f16 implementation and the previous behavior (fallback to reference).
(Note: Only collected FWD_D cases)
speedup_ratio.csv
with_f16_softmax.csv
without_f16_softmax.csv
Average Speedup: ~23.40x