Ideas

Make monitor and cpu modules truly share the uart with monitor taking precedence. So monitor will not wait for the hlt signal from the cpu but go ahead while eavedropping on rx to see if a <brk> / <nul> char is seen and then halt the cpu.

Implemented this at the SoC level : a uart receive error (which in this uart is also triggered by an incoming break) is wired to force control back to the monitor. That doesn't actually halt the cpu but in most cases that is ok.

Research needed: on a statement like C <= C + 1 what kind of adder is generated (ripple, or carry look ahead)? Because i get some weird results if a LDIC follows a LDICP, with some other op inbetween it works ok, but without it it doesn't.

Research needed: on a case statement with a default, why does it matter what the bit patterns are on how many LUTs are used