[BUG] MM LRU cache fixing

[vadiklyutiy]

We keep 2 MM caches in Client/Frontend and Server/EngineCore (see detailed description in the top of /vllm/v1/engine/mm_input_cache.py ).

In case on cache hit on Client side we didn't update access time because did only in that not update access time by design. On Server side we make explicit access. In result LRU order was inconsistent and over time, the cache content also became inconsistent.

This PR add dummy access on Client side to keep access times consistent.

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[DarkLight1337]

Thanks, I have already opened a PR #16593 to fix this though