VLSI lab - PoliTO
VLSI lab @ Dipartimento di Elettronica e Telecomunicazioni (DET) in Politecnico di Torino
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Mage-and-Rogue
Mage-and-Rogue PublicTemplate-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
Python 7
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- area-plot-post-syn Public
vlsi-lab/area-plot-post-syn’s past year of commit activity - keccak Public
vlsi-lab/keccak’s past year of commit activity - Mage-and-Rogue Public
Template-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
vlsi-lab/Mage-and-Rogue’s past year of commit activity - compact-yet-fast-ascon Public
SystemVerilog RTL of a compact, d-order masked ASCON with reconfigurable masking for higher throughput.
vlsi-lab/compact-yet-fast-ascon’s past year of commit activity - HORCRUX Public
vlsi-lab/HORCRUX’s past year of commit activity
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