Merge branch 'develop' into 'main'

Added racetrack memory possibility to the Riscv core

See merge request racetrack-logic/risc-v-lim-architecture!10

Author: f-riente

.gitignore

@@ -20,3 +20,8 @@ TAGS
 /Bender.local
 work/
 transcript
+.gitlab-ci.yml.*
+RI5CY-sameIF/tb/core/simv
+RI5CY-sameIF/tb/core/simv.daidir/
+RI5CY-sameIF/tb/core/ucli.key
+RI5CY-sameIF/tb/core/csrc/

.gitlab-ci.yml

@@ -0,0 +1,21 @@
+stages:
+ - vsim_mem_std_mode0
+# - vcs_lim_mem
+
+build_vsim_mem_std_mode0:
+ stage: vsim_mem_std_mode0
+ tags: [eda_tools]
+ script:
+  - git submodule update --remote RI5CY-sameIF/rtl/fpnew
+  - cd RI5CY-sameIF/tb/core
+  - source /eda/scripts/init_questa_core_prime
+  - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=0 MEM_TYPE=STD_MEM custom-vsim-run
+
+#build_vcs_lim_mem:
+# stage: vcs_lim_mem
+# tags: [eda_tools]
+# script:
+#  - git submodule update --remote RI5CY-sameIF/rtl/fpnew
+#  - cd RI5CY-sameIF/tb/core
+#  - source /eda/scripts/init_synopsys_vcs
+#  - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=0 MEM_TYPE=RT_LIM_MEM vcs-run-bitwise-ext-asm

README.md

@@ -18,6 +18,9 @@ when it has been contributed to [OpenHW Group](https://www.openhwgroup.org/).
 ## RISC-V with the same interface
 The RI5CY-sameIF repository contains the CV32E40P/RISC-V IP that supports Logic-in-memory operations, that mantains the same original interface in order to prioritise the flexibility of the core.
 
+## RISC-V with the new interface
+The RI5CY-newIF repository contains the CV32E40P/RISC-V IP that supports Logic-in-memory operations, that has a new interface to maximise the efficiency of the memory operations.
+
 
 # Prerequisites
 Clone the current repository
@@ -39,7 +42,19 @@ Build the toolchain:
 Where N is the number of threads.
 
 # Usage
-Enter the directory `RI5CY-sameIF/tb/core` and modify the makefile. In particular, change the variable `RISCV_LIB` with your `<tool_chain_install_path>` previously used in the configuration.
+Enter the directory `RI5CY-sameIF/tb/core` and modify the Makefile. In particular, change the variable `RISCV_LIB` with your `<tool_chain_install_path>` previously used in the configuration.
+
+Modify variable `MEM_TYPE` inside the Makefile to build the desired memory type.
+Available memories:
+- Standard memory (STD_MEM)
+- Standard memory with LiM functionalities (LIM_MEM)
+- Racetrack memory with LiM functionalities (RT_LIM_MEM)
+
+Racetrack memory supports two different modes, set the correct parameter `MEM_MODE` in file `RI5CY-sameIF/tb/core/tb_tob.sv` to choose the wanted configuration:
+- Memory mode (MEM_MODE = 0)
+- LiM mode    (MEM_MODE = 1)
+
+
 
 For executing a sample program run:
 
@@ -49,3 +64,5 @@ For executing a sample program run:
 
 
 
+
+

RI5CY-sameIF/rtl/include/riscv_defines.sv

@@ -73,14 +73,19 @@ parameter REGC_ZERO = 2'b11;
 // LOGIC-IN-MEMORY custom
 parameter OPCODE_STORE_ACTIVE_LOGIC  = 7'h3b;
 parameter OPCODE_LOAD_MASK           = 7'h1b;
-
-parameter FUNCT_NONE = 3'b000;
-parameter FUNCT_XOR  = 3'b001;
-parameter FUNCT_AND  = 3'b010;
-parameter FUNCT_OR   = 3'b011;
-parameter FUNCT_MIN  = 3'b101;
-parameter FUNCT_MAX  = 3'b110;
-
+parameter WAIT_LIM_CYCLES   		 = 2;
+
+
+//Extended funct parameters for new store_active
+parameter FUNCT_NONE = 8'b00000000;
+parameter FUNCT_XOR  = 8'b00000001;
+parameter FUNCT_AND  = 8'b00000010;
+parameter FUNCT_OR   = 8'b00000011;
+parameter FUNCT_NAND = 8'b00001010;
+parameter FUNCT_NOR  = 8'b00001011;
+parameter FUNCT_XNOR = 8'b00001001;
+parameter FUNCT_MIN  = 8'b00000101;
+parameter FUNCT_MAX  = 8'b00000110;
 //////////////////////////////////////////////////////////////////////////////
 //      _    _    _   _    ___                       _   _                  //
 //     / \  | |  | | | |  / _ \ _ __   ___ _ __ __ _| |_(_) ___  _ __  ___  //

RI5CY-sameIF/rtl/riscv_decoder.sv

@@ -442,7 +442,8 @@ module riscv_decoder
         alu_op_c_mux_sel_o  = OP_C_LIM_FUNCT;
         // offset from immediate
         alu_operator_o      = ALU_ADD;
-        imm_b_mux_sel_o     = IMMB_I;
+        //take as immediate the one used in load_mask
+        imm_b_mux_sel_o     = IMMB_LOGMEM;
         alu_op_b_mux_sel_o  = OP_B_IMM;
         // store size
         data_type_o = 2'b00; // SW

RI5CY-sameIF/rtl/riscv_id_stage.sv

@@ -783,8 +783,7 @@ module riscv_id_stage
   end
 
   // Logic-in-memory operator
-  assign logic_in_memory_funct = {operand_c_fw_id[28:0], instr[14:12]};
-
+  assign logic_in_memory_funct = {operand_c_fw_id[23:0],instr[24:20], instr[14:12]};
 
   ///////////////////////////////////////////////////////////////////////////
   //  ___                              _ _       _              ___ ____   //