feat(cuda): single-pass dispatch plan builder

[0ax1]

Refactor the dynamic dispatch plan builder to walk the encoding tree exactly once, discovering unfusable subtrees and computing shared memory requirements in the same pass. The result is a 3-variant enum (Fused, PartiallyFused, Unfusable) that replaces the previous Result<Option<>> API and eliminates the separatefind_unfusable_nodes traversal.

Shared memory is now validated upfront in DispatchPlan::new - before any subtree kernels are executed - so we never pay GPU cost for a plan that will not fit.

The plan stages are split into smem_stages (fully decoded into persistent shared memory) and output_stage (tiled through a scratch region), making the two-phase kernel execution model explicit in the host-side data structures. Shared memory allocation invariants are documented on FusedPlan.

[codspeed-hq]

Merging this PR will degrade performance by 15.51%

❌ 2 regressed benchmarks
✅ 1104 untouched benchmarks
⏩ 1522 skipped benchmarks¹

⚠️ Please fix the performance issues or acknowledge them on CodSpeed.

Performance Changes

	Mode	Benchmark	BASE	HEAD	Efficiency
❌	Simulation	bitwise_not_vortex_buffer_mut[1024]	477.2 ns	535.6 ns	-10.89%
❌	Simulation	bitwise_not_vortex_buffer_mut[128]	317.8 ns	376.1 ns	-15.51%

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_{Comparing ad/cuda-next (b4adfcd) with develop (d0ed3fc)}

Footnotes

1. 1522 benchmarks were skipped, so the baseline results were used instead. If they were deleted from the codebase, click here and archive them to remove them from the performance reports. ↩

[0ax1]

Right now we're loading all dict values and all runend ends & codes into GPU shared memory. I didn't change this as part of this PR to scope it. But in a follow up I want to change the logic to tile/window through dict and runed with a fixed shared memory budget. In case of dict, this might be based on some LRU cache indirection or similar.