This example program demonstrates fault injection handling on a dual-core processor architecture using soft Mi-V processors. An interrupt is triggered in one of the Mi-V processors, leading to a fault condition. The system is then reset as a response to the fault condition triggered.
This project provides two build configurations for SoftConsole, miv-rv32-imc-debug and miv-rv32-imc-release.
The project is tested on the PolarFire Icicle Kit with the following hardware design.
Hardware configurations are defined in the fpga_design_config.h header file inside the boards directory. Changes might be necessary for different hardware configurations.