Hello hello!

module top_module (
    input clk,
    input reset,
    output [9:0] q);
	
    always_ff@(posedge clk) begin
        if(reset || q == 999) begin
            q <= 0;
        end
        else begin
            q <= q + 1;
        end
    end
endmodule

Languages and tools I am familiar with