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Merged
dgarske merged 2 commits into from
Jun 20, 2025
Merged

PPC 32 ASM: SHA-256 #8894

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c39f1fe
PPC 32 ASM: SHA-256
SparkiDev Jun 18, 2025
62721f4
PPC32 SHA-256 ASM: small code implementation
SparkiDev Jun 19, 2025
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63 changes: 63 additions & 0 deletions configure.ac
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Original file line number Diff line number Diff line change
Expand Up @@ -1211,6 +1211,11 @@ then
AC_MSG_ERROR([--enable-all-asm is incompatible with --disable-armasm])
fi

if test "$enable_ppc32_asm" = "no"
then
AC_MSG_ERROR([--enable-all-asm is incompatible with --disable-ppc32-asm])
fi

case "$host_cpu" in
*x86_64*|*amd64*)
if test "$enable_intelasm" = ""
Expand Down Expand Up @@ -1240,6 +1245,14 @@ then
fi
fi
;;
*powerpc64*)
;;
*powerpc*)
if test "$enable_ppc32_asm" = ""
then
enable_ppc32_asm=yes
fi
;;
esac
fi

Expand Down Expand Up @@ -3488,6 +3501,49 @@ do
done


# PPC32 Assembly
AC_ARG_ENABLE([ppc32-asm],
[AS_HELP_STRING([--enable-ppc32-asm],[Enable wolfSSL PowerPC 32-bit ASM support (default: disabled).])],
[ ENABLED_PPC32_ASM=$enableval ],
[ ENABLED_PPC32_ASM=no ]
)


if test "$ENABLED_PPC32_ASM" != "no" && test "$ENABLED_ASM" = "yes"
then
ENABLED_PPC32_ASM_OPTS=$ENABLED_PPC32_ASM
for v in `echo $ENABLED_PPC32_ASM_OPTS | tr "," " "`
do
case $v in
yes)
;;
inline)
ENABLED_PPC32_ASM_INLINE=yes
;;
small)
ENABLED_PPC32_ASM_SMALL=yes
;;
*)
AC_MSG_ERROR([Invalid RISC-V option [yes,inline,small]: $ENABLED_PPC32_ASM.])
break
;;
esac
done

AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM"
AC_MSG_NOTICE([32-bit PowerPC assembly for SHA-256])
ENABLED_PPC32_ASM=yes
fi
if test "$ENABLED_PPC32_ASM_INLINE" = "yes"; then
AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_INLINE"
else
AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM"
fi
if test "$ENABLED_PPC32_ASM_SMALL" = "yes"; then
AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_PPC32_ASM_SMALL"
fi

# Xilinx hardened crypto
AC_ARG_ENABLE([xilinx],
[AS_HELP_STRING([--enable-xilinx],[Enable wolfSSL support for Xilinx hardened crypto(default: disabled)])],
Expand Down Expand Up @@ -10564,6 +10620,8 @@ AM_CONDITIONAL([BUILD_ARM_NONTHUMB],[test "$ENABLED_ARM_THUMB" != "yes" || test
AM_CONDITIONAL([BUILD_ARM_32],[test "$ENABLED_ARM_32" = "yes" || test "$ENABLED_USERSETTINGS" = "yes"])
AM_CONDITIONAL([BUILD_ARM_64],[test "$ENABLED_ARM_64" = "yes" || test "$ENABLED_USERSETTINGS" = "yes"])
AM_CONDITIONAL([BUILD_RISCV_ASM],[test "x$ENABLED_RISCV_ASM" = "xyes"])
AM_CONDITIONAL([BUILD_PPC32_ASM],[test "x$ENABLED_PPC32_ASM" = "xyes"])
AM_CONDITIONAL([BUILD_PPC32_ASM_INLINE],[test "x$ENABLED_PPC32_ASM_INLINE" = "xyes"])
AM_CONDITIONAL([BUILD_XILINX],[test "x$ENABLED_XILINX" = "xyes"])
AM_CONDITIONAL([BUILD_AESNI],[test "x$ENABLED_AESNI" = "xyes"])
AM_CONDITIONAL([BUILD_INTELASM],[test "x$ENABLED_INTELASM" = "xyes"])
Expand Down Expand Up @@ -11217,6 +11275,11 @@ echo " * ARM ASM: $ENABLED_ARMASM"
echo " * ARM ASM SHA512/SHA3 Crypto $ENABLED_ARMASM_SHA3"
echo " * ARM ASM SM3/SM4 Crypto $ENABLED_ARMASM_CRYPTO_SM4"
echo " * RISC-V ASM $ENABLED_RISCV_ASM"
if test "$ENABLED_PPC32_ASM_INLINE" = "yes"
then
ENABLED_PPC32_ASM="inline C"
fi
echo " * PPC32 ASM $ENABLED_PPC32_ASM"
echo " * Write duplicate: $ENABLED_WRITEDUP"
echo " * Xilinx Hardware Acc.: $ENABLED_XILINX"
echo " * C89: $ENABLED_C89"
Expand Down
25 changes: 25 additions & 0 deletions src/include.am
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Original file line number Diff line number Diff line change
Expand Up @@ -251,10 +251,19 @@ endif !BUILD_X86_ASM
endif !BUILD_ARMASM
endif !BUILD_ARMASM_NEON


if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha256.c
endif BUILD_RISCV_ASM

if BUILD_PPC32_ASM
if BUILD_PPC32_ASM_INLINE
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm_c.c
else
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm.S
endif !BUILD_PPC32_ASM_INLINE
endif BUILD_PPC32_ASM

if BUILD_SHA512
if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha512.c
Expand Down Expand Up @@ -455,6 +464,14 @@ if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha256.c
endif BUILD_RISCV_ASM

if BUILD_PPC32_ASM
if BUILD_PPC32_ASM_INLINE
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm_c.c
else
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm.S
endif !BUILD_PPC32_ASM_INLINE
endif BUILD_PPC32_ASM

if BUILD_SHA512
if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha512.c
Expand Down Expand Up @@ -718,6 +735,14 @@ if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha256.c
endif BUILD_RISCV_ASM

if BUILD_PPC32_ASM
if BUILD_PPC32_ASM_INLINE
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm_c.c
else
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/ppc32/ppc32-sha256-asm.S
endif !BUILD_PPC32_ASM_INLINE
endif BUILD_PPC32_ASM

endif !BUILD_FIPS_CURRENT

if BUILD_AFALG
Expand Down
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