GitHub - xicer-hub/ECE441-Project-2: Verilog code for synchronous 50,000,000:1 clock divider, 4 bit up counter, and seven segment decoder.

ECE441-Project-2

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
.gitignore		.gitignore
4bit_counter.v		4bit_counter.v
4bit_counter_tb.v		4bit_counter_tb.v
LICENSE.md		LICENSE.md
README.md		README.md
clock_divider.v		clock_divider.v
clock_divider_tb.v		clock_divider_tb.v
main.v		main.v
sev_seg_decoder.v		sev_seg_decoder.v
sev_seg_decoder_tb.v		sev_seg_decoder_tb.v

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