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14 changes: 11 additions & 3 deletions src/Language/SystemVerilog/Parser/Parse.y
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ import Language.SystemVerilog.Parser.Tokens
%tokentype { Token }
%error { parseErrorTok }

%expect 0
%expect 4
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It looks like this introduces shift/reduce conflicts, meaning there is ambiguity in the grammar. I'm going to see if there is a way to add this feature without the conflicts.


%token

Expand Down Expand Up @@ -947,9 +947,17 @@ ImportOrExport :: { [PackageItem] }
: "import" PackageImportItems ";" { map (uncurry Import) $2 }
| "export" PackageImportItems ";" { map (uncurry Export) $2 }
| "export" "*" "::" "*" ";" { [Export "" ""] }
BlockItemDecls :: { [Decl] }
: {- empty -} { [] }
| ";" BlockItemDecls { $2 }
| BlockItemDecl BlockItemDecls { $1 ++ $2 }
BlockItemDecl :: { [Decl] }
: DataDecl { $1 }
DataDecl :: { [Decl] }
: Typedef { [$1] }
TaskOrFunction :: { PackageItem }
: "function" Lifetime FuncRetAndName TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) }
| "task" Lifetime Identifier TFItems DeclsAndStmts endtask StrTag {% checkTag $3 $7 $ Task $2 $3 ($4 ++ fst $5) (snd $5) }
: "function" Lifetime FuncRetAndName TFItems BlockItemDecls DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $8 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ $5 ++ fst $6) (snd $6) }
| "task" Lifetime Identifier TFItems BlockItemDecls DeclsAndStmts endtask StrTag {% checkTag $3 $8 $ Task $2 $3 ($4 ++ $5 ++ fst $6) (snd $6) }
Typedef :: { Decl }
: "typedef" Type Identifier ";" { ParamType Localparam $3 $2 }
| "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) }
Expand Down
12 changes: 12 additions & 0 deletions test/core/tf_typedef.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
module top;
task t;
typedef bit u;
$display("t = %d", u'(0));
endtask
function f;
typedef bit u;
return u'(1);
endfunction
initial t();
initial $display("f = %d", f());
endmodule
11 changes: 11 additions & 0 deletions test/core/tf_typedef.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
module top;
task t;
$display("t = %d", 1'd0);
endtask
function f;
input reg _sv2v_unused;
f = 1'd1;
endfunction
initial t;
initial $display("f = %d", f(0));
endmodule