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gd32 usb #32

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0a5e51e
gd32f4xx: upgrade to v3.0.3
cameled Feb 25, 2023
e5c45f4
gd32f4xx: Patch firmware 3.0.3
cameled Feb 25, 2023
8790803
gd32f4xx: add usb hal
cameled Mar 1, 2023
a682383
scripts: gd32headers support usb headers
cameled Mar 1, 2023
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15 changes: 15 additions & 0 deletions common_include/gd32_usb.h
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@@ -0,0 +1,15 @@
/*
* NOTE: Autogenerated file using gd32headers.py
*
* SPDX-License-Identifier: Apache-2.0
*/

#if defined(CONFIG_SOC_SERIES_GD32F4XX)
#include <drv_usb_dev.h>
#include <drv_usb_regs.h>
#include <drv_usbd_int.h>
#include <drv_usbh_int.h>
#include <drv_usb_core.h>
#include <drv_usb_hw.h>
#include <drv_usb_host.h>
#endif
4 changes: 2 additions & 2 deletions gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h
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Expand Up @@ -195,9 +195,9 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#ifndef BIT
#ifndef BIT
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#endif /* BIT */
#endif /* BIT */

#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
Expand Down
22 changes: 15 additions & 7 deletions gd32f4xx/cmsis/gd/gd32f4xx/source/system_gd32f4xx.c
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Expand Up @@ -56,14 +56,21 @@
//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000)
//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000)

#define RCU_MODIFY(__delay) do{ \
volatile uint32_t i; \
if(0 != __delay){ \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
for(i=0; i<__delay; i++){ \
} \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
for(i=0; i<__delay; i++){ \
} \
} \
}while(0)

#define SEL_IRC16M 0x00U
#define SEL_HXTAL 0x01U
#define SEL_PLLP 0x02U
#define RCU_MODIFY {volatile uint32_t i; \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
for(i=0;i<50000;i++); \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
for(i=0;i<50000;i++);}

/* set the system clock frequency and declare the system clock configuration function */
#ifdef __SYSTEM_CLOCK_IRC16M
Expand Down Expand Up @@ -129,8 +136,9 @@ void SystemInit (void)
/* Reset the RCU clock configuration to the default reset state */
/* Set IRC16MEN bit */
RCU_CTL |= RCU_CTL_IRC16MEN;

RCU_MODIFY
while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
}
RCU_MODIFY(0x50);

RCU_CFG0 &= ~RCU_CFG0_SCS;

Expand Down
566 changes: 283 additions & 283 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_adc.h
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4 changes: 2 additions & 2 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_can.h
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Expand Up @@ -406,8 +406,8 @@ typedef struct {
ControlStatus time_triggered; /*!< time triggered communication mode */
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
ControlStatus auto_retrans; /*!< automatic retransmission mode disable */
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode disable */
ControlStatus auto_retrans; /*!< automatic retransmission mode */
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
uint16_t prescaler; /*!< baudrate prescaler */
} can_parameter_struct;
Expand Down
8 changes: 0 additions & 8 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_ctc.h
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Expand Up @@ -65,7 +65,6 @@ OF SUCH DAMAGE.
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */

/* CTC_STAT */
Expand Down Expand Up @@ -94,15 +93,10 @@ OF SUCH DAMAGE.
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/

/* USBFS or USBHS SOF signal selection definitions */
#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/
#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/

/* reference signal source selection definitions */
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */

/* reference signal source prescaler definitions */
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
Expand Down Expand Up @@ -156,8 +150,6 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode);

/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t polarity);
/* select USBFS or USBHS SOF signal */
void ctc_usbsof_signal_select(uint32_t usbsof);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t refs);
/* configure reference signal source prescaler */
Expand Down
4 changes: 2 additions & 2 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_enet.h
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Expand Up @@ -124,7 +124,7 @@ OF SUCH DAMAGE.
#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */
#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */
#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */
#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */
#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */
#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */
#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */
#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */
Expand Down Expand Up @@ -1113,7 +1113,7 @@ typedef struct
#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */
#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */

#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */

Expand Down
11 changes: 7 additions & 4 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_exmc.h
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Expand Up @@ -6,6 +6,7 @@
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
\version 2022-06-08, V3.0.1, firmware for GD32F4xx
*/

/*
Expand Down Expand Up @@ -208,7 +209,7 @@ OF SUCH DAMAGE.
/* EXMC_SDARI */
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */
#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */

/* EXMC_SDSTAT */
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
Expand Down Expand Up @@ -330,7 +331,7 @@ typedef struct
{
uint32_t sdram_device; /*!< device of SDRAM */
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
uint32_t brust_read_switch; /*!< enable or disable the burst read */
uint32_t burst_read_switch; /*!< enable or disable the burst read */
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
Expand Down Expand Up @@ -718,7 +719,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region);
/* NAND */
/* deinitialize EXMC NAND bank */
void exmc_nand_deinit(uint32_t exmc_nand_bank);
/* initialize exmc_norsram_parameter_struct with the default values */
/* initialize exmc_nand_parameter_struct with the default values */
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
/* initialize EXMC NAND bank */
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
Expand All @@ -744,6 +745,8 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device);
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
/* initialize EXMC SDRAM device */
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
/* initialize exmc_sdram_command_parameter_struct with the default values */
void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct);
/* SQPIPSRAM */
/* deinitialize EXMC SQPIPSRAM */
void exmc_sqpipsram_deinit(void);
Expand Down Expand Up @@ -774,7 +777,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_c
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
/* set the number of successive auto-refresh command */
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
/* config the write protection function */
/* configure the write protection function */
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
/* get the status of SDRAM device0 or device1 */
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
Expand Down
77 changes: 37 additions & 40 deletions gd32f4xx/standard_peripheral/include/gd32f4xx_exti.h
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Expand Up @@ -177,34 +177,33 @@ OF SUCH DAMAGE.
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */

/* EXTI_PD */
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */
#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */
#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */

/* constants definitions */
/* EXTI line number */
typedef enum
{
typedef enum {
EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */
Expand All @@ -227,29 +226,27 @@ typedef enum
EXTI_19 = BIT(19), /*!< EXTI line 19 */
EXTI_20 = BIT(20), /*!< EXTI line 20 */
EXTI_21 = BIT(21), /*!< EXTI line 21 */
EXTI_22 = BIT(22), /*!< EXTI line 22 */
}exti_line_enum;
EXTI_22 = BIT(22) /*!< EXTI line 22 */
} exti_line_enum;

/* external interrupt and event */
typedef enum
{
typedef enum {
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
}exti_mode_enum;
} exti_mode_enum;

/* interrupt trigger mode */
typedef enum
{
typedef enum {
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_NONE /*!< none EXTI edge trigger */
}exti_trig_type_enum;
} exti_trig_type_enum;

/* function declarations */
/* deinitialize the EXTI */
void exti_deinit(void);
/* enable the configuration of EXTI initialize */
/* initialize the EXTI line x */
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
Expand All @@ -259,19 +256,19 @@ void exti_interrupt_disable(exti_line_enum linex);
void exti_event_enable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* EXTI software interrupt event enable */
/* enable the software interrupt event from EXTI line x */
void exti_software_interrupt_enable(exti_line_enum linex);
/* EXTI software interrupt event disable */
/* disable the software interrupt event from EXTI line x */
void exti_software_interrupt_disable(exti_line_enum linex);

/* interrupt & flag functions */
/* get EXTI lines pending flag */
/* get EXTI line x interrupt pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
/* clear EXTI line x interrupt pending flag */
void exti_flag_clear(exti_line_enum linex);
/* get EXTI lines flag when the interrupt flag is set */
/* get EXTI line x interrupt pending flag */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
/* clear EXTI line x interrupt pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);

#endif /* GD32F4XX_EXTI_H */
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