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s32: drivers: s32ze: update drivers to RTD 2.0.1
Update headers and baremetal drivers device to NXP S32 RTD 2.0.1 Signed-off-by: Tu Nguyen Van <[email protected]>
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‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip.h

Lines changed: 16 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2021-2024 NXP
2+
* Copyright 2021-2025 NXP
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -36,7 +36,7 @@ extern "C"{
3636
#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION 0
3737
#define ADC_SAR_IP_SW_MAJOR_VERSION 2
3838
#define ADC_SAR_IP_SW_MINOR_VERSION 0
39-
#define ADC_SAR_IP_SW_PATCH_VERSION 0
39+
#define ADC_SAR_IP_SW_PATCH_VERSION 1
4040

4141
/*==================================================================================================
4242
* FILE VERSION CHECKS
@@ -242,21 +242,6 @@ void Adc_Sar_Ip_EnableChannel(const uint32 u32Instance,
242242
void Adc_Sar_Ip_DisableChannel(const uint32 u32Instance,
243243
const Adc_Sar_Ip_ConvChainType pChainType,
244244
const uint32 u32ChnIdx);
245-
246-
#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
247-
/*!
248-
* @brief Set conversion resolution
249-
*
250-
* This function sets the conversion resolution (number of bits per conversion data)
251-
*
252-
* @param[in] u32Instance - ADC instance number
253-
* @param[in] eResolution - conversion resolution
254-
* @return void
255-
*/
256-
void Adc_Sar_Ip_SetResolution(const uint32 u32Instance,
257-
const Adc_Sar_Ip_Resolution eResolution);
258-
#endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
259-
260245
/*!
261246
* @brief Start conversion
262247
*
@@ -368,13 +353,15 @@ void Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,
368353
const Adc_Sar_Ip_ConvChainType pChainType,
369354
Adc_Sar_Ip_ChanResultType * const pResult);
370355

356+
357+
#if ADC_SAR_IP_CALIBRATION_AVAILABLE
371358
/*!
372359
* @brief Perform Calibration of the ADC
373360
*
374361
* This function performs a calibration of the ADC. The maximum input clock
375362
* frequency for the ADC is 80 MHz, checked with assertions if DEV_ASSERT is
376363
* enabled. After calibration, the ADC is left in Powerup state (PWDN bit is clear).
377-
* Note: If asynchronous calibration mode is enabled and a calibration is started,
364+
* Note: If asynchronous calibration mode is enabled and a calibration is started,
378365
* other APIs should not be called until the calibration is complete.
379366
*
380367
* @param[in] u32Instance - ADC instance number
@@ -386,6 +373,7 @@ void Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,
386373
*/
387374
Adc_Sar_Ip_StatusType Adc_Sar_Ip_DoCalibration(const uint32 u32Instance);
388375

376+
#endif /* ADC_SAR_IP_CALIBRATION_AVAILABLE */
389377
/*!
390378
* @brief Power up the ADC
391379
*
@@ -490,7 +478,7 @@ void Adc_Sar_Ip_DisableChannelNotifications(const uint32 u32Instance,
490478
Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,
491479
const Adc_Sar_Ip_ClockConfigType * const pConfig);
492480

493-
#if FEATURE_ADC_HAS_CONVERSION_TIMING
481+
#if ADC_SAR_IP_CONVERSION_TIMING_AVAILABLE
494482
/*!
495483
* @brief Set the sample times
496484
*
@@ -504,9 +492,9 @@ Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,
504492
*/
505493
void Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,
506494
const uint8 * const aSampleTimes);
507-
#endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
495+
#endif /* ADC_SAR_IP_CONVERSION_TIMING_AVAILABLE */
508496

509-
#if FEATURE_ADC_HAS_AVERAGING
497+
#if ADC_SAR_IP_AVERAGING_AVAILABLE
510498
/*!
511499
* @brief Configure averaging
512500
*
@@ -522,7 +510,7 @@ void Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,
522510
void Adc_Sar_Ip_SetAveraging(const uint32 u32Instance,
523511
const boolean bAvgEn,
524512
const Adc_Sar_Ip_AvgSelectType eAvgSel);
525-
#endif /* FEATURE_ADC_HAS_AVERAGING */
513+
#endif /* ADC_SAR_IP_AVERAGING_AVAILABLE */
526514

527515
/*!
528516
* @brief Abort ongoing conversion
@@ -554,7 +542,7 @@ Adc_Sar_Ip_StatusType Adc_Sar_Ip_AbortChain(const uint32 u32Instance,
554542
const boolean bBlocking,
555543
const boolean bAllowRestart);
556544

557-
#if FEATURE_ADC_HAS_PRESAMPLING
545+
#if ADC_SAR_IP_PRESAMPLING_AVAILABLE
558546
/*!
559547
* @brief Set the Presampling Source for the channel group
560548
*
@@ -614,7 +602,7 @@ void Adc_Sar_Ip_EnablePresampleConversion(const uint32 u32Instance);
614602
* @return void
615603
*/
616604
void Adc_Sar_Ip_DisablePresampleConversion(const uint32 u32Instance);
617-
#endif /* FEATURE_ADC_HAS_PRESAMPLING */
605+
#endif /* ADC_SAR_IP_PRESAMPLING_AVAILABLE */
618606

619607
/*!
620608
* @brief Enable DMA Requests
@@ -732,7 +720,7 @@ Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,
732720
#endif /* ADC_SAR_IP_HAS_CTU */
733721

734722
#if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
735-
#if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
723+
#if (ADC_SAR_IP_INJ_EXT_TRIGGER_AVAILABLE || ADC_SAR_IP_EXT_TRIGGER_AVAILABLE)
736724
/*!
737725
* @brief Configure external trigger
738726
*
@@ -746,9 +734,10 @@ Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,
746734
void Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,
747735
const Adc_Sar_Ip_ExtTriggerEdgeType eTriggerEdge,
748736
const Adc_Sar_Ip_ExtTriggerSourceType eTrggerSrc);
749-
#endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
737+
#endif /* (ADC_SAR_IP_INJ_EXT_TRIGGER_AVAILABLE || ADC_SAR_IP_EXT_TRIGGER_AVAILABLE) */
750738
#endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
751739

740+
#if ADC_SAR_IP_USER_OFFSET_GAIN_REG_AVAILABLE
752741
/*!
753742
* @brief Configure user gain and offset
754743
*
@@ -762,6 +751,7 @@ void Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,
762751
void Adc_Sar_Ip_SetUserGainAndOffset(const uint32 Instance,
763752
const uint16 Gain,
764753
const uint8 Offset);
754+
#endif /* ADC_SAR_IP_USER_OFFSET_GAIN_REG_AVAILABLE */
765755

766756

767757
#define ADC_STOP_SEC_CODE

‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip_HeaderWrapper_S32XX.h

Lines changed: 43 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2021-2024 NXP
2+
* Copyright 2021-2025 NXP
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -30,7 +30,7 @@ extern "C"{
3030
#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32XX 0
3131
#define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32XX 2
3232
#define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32XX 0
33-
#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX 0
33+
#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX 1
3434

3535
/*==================================================================================================
3636
* DEFINITIONS
@@ -86,50 +86,50 @@ extern "C"{
8686
#define ADC_SAR_IP_ABORTCHAIN_WORKAROUND (1U)
8787

8888
#if (ADC_SAR_IP_INSTANCE_COUNT == 2U)
89-
/* 31-28 3-0 63-60 35-32 95-92 67-64
90-
\_/ \_/ \_/ \_/ \_/ \_/
91-
|......| |......| |......| */
92-
#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
93-
{0x000000FFU, 0x00000079U}, /* 1 */ \
94-
}
95-
/* Adc Channels are divided into 2 Groups. */
96-
/* This array shows max number of channels of each group. */
97-
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
98-
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
99-
#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
100-
{8U, 8U}, /* 1 */ \
101-
}
102-
/* Number of group channels of each unit*/
103-
/* Unit 0 / 1 */
104-
#define FEATURE_ADC_MAX_GROUP_COUNT { 2U, 2U }
105-
/* Bit0: DSDR is available
106-
Bit1: PSCR is available
107-
Bit2: CTU is available
108-
Bit3: CTU trigger mode is available */
109-
#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
110-
0x0000000EU, /* 1 */ \
111-
}
112-
#else
113-
/* 31-28 3-0 63-60 35-32 95-92 67-64
114-
\_/ \_/ \_/ \_/ \_/ \_/
115-
|......| |......| |......| */
116-
#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
117-
}
118-
/* Adc Channels are divided into 2 Groups. */
119-
/* This array shows max number of channels of each group. */
120-
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
121-
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
122-
#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
123-
}
124-
/* Number of group channels of each unit*/
125-
/* Unit 0 */
126-
#define FEATURE_ADC_MAX_GROUP_COUNT { 2U }
127-
/* Bit0: DSDR is available
89+
/* 31-28 3-0 63-60 35-32 95-92 67-64
90+
\_/ \_/ \_/ \_/ \_/ \_/
91+
|......| |......| |......| */
92+
#define ADC_SAR_IP_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
93+
{0x000000FFU, 0x00000079U}, /* 1 */ \
94+
}
95+
/* Adc Channels are divided into 2 Groups. */
96+
/* This array shows max number of channels of each group. */
97+
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
98+
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
99+
#define ADC_SAR_IP_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
100+
{8U, 8U}, /* 1 */ \
101+
}
102+
/* Number of group channels of each unit*/
103+
/* Unit 0 / 1 */
104+
#define ADC_SAR_IP_MAX_GROUP_COUNT { 2U, 2U }
105+
/* Bit0: DSDR is available
128106
Bit1: PSCR is available
129107
Bit2: CTU is available
130108
Bit3: CTU trigger mode is available */
131-
#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
132-
}
109+
#define ADC_SAR_IP_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
110+
0x0000000EU, /* 1 */ \
111+
}
112+
#else
113+
/* 31-28 3-0 63-60 35-32 95-92 67-64
114+
\_/ \_/ \_/ \_/ \_/ \_/
115+
|......| |......| |......| */
116+
#define ADC_SAR_IP_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
117+
}
118+
/* Adc Channels are divided into 2 Groups. */
119+
/* This array shows max number of channels of each group. */
120+
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
121+
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
122+
#define ADC_SAR_IP_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
123+
}
124+
/* Number of group channels of each unit*/
125+
/* Unit 0 */
126+
#define ADC_SAR_IP_MAX_GROUP_COUNT { 2U }
127+
/* Bit0: DSDR is available
128+
Bit1: PSCR is available
129+
Bit2: CTU is available
130+
Bit3: CTU trigger mode is available */
131+
#define ADC_SAR_IP_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
132+
}
133133
#endif /* (ADC_SAR_IP_INSTANCE_COUNT == 2U) */
134134

135135
/* Register access defines */

‎s32/drivers/s32ze/Adc/include/Adc_Sar_Ip_HeaderWrapper_S32XX_AE.h

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2021-2024 NXP
2+
* Copyright 2021-2025 NXP
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -30,7 +30,7 @@ extern "C"{
3030
#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32XX_AE 0
3131
#define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32XX_AE 2
3232
#define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32XX_AE 0
33-
#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX_AE 0
33+
#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX_AE 1
3434

3535
/*==================================================================================================
3636
* DEFINITIONS
@@ -88,44 +88,44 @@ extern "C"{
8888

8989
#define ADC_SAR_IP_ABORTCHAIN_WORKAROUND (1U)
9090

91-
/* 31-28 3-0 63-60 35-32 95-92 67-64
92-
\_/ \_/ \_/ \_/ \_/ \_/
93-
|......| |......| |......| */
94-
#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
95-
{0x000000FFU, 0x00000079U}, /* 1 */ \
96-
{0x00FFFFFFU, 0x00000000U}, /* 2 (ADC_AE_0_0) */ \
97-
{0x00001FFFU, 0x00000000U}, /* 3 (ADC_AE_1_0) */ \
98-
{0x00001FFFU, 0x00000000U}, /* 4 (ADC_AE_1_1) */ \
99-
{0x00001FFFU, 0x00000000U}, /* 5 (ADC_AE_2_0) */ \
100-
{0x00001FFFU, 0x00000000U}, /* 6 (ADC_AE_2_1) */ \
91+
/* 31-28 3-0 63-60 35-32 95-92 67-64
92+
\_/ \_/ \_/ \_/ \_/ \_/
93+
|......| |......| |......| */
94+
#define ADC_SAR_IP_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \
95+
{0x000000FFU, 0x00000079U}, /* 1 */ \
96+
{0x00FFFFFFU, 0x00000000U}, /* 2 (ADC_AE_0_0) */ \
97+
{0x00001FFFU, 0x00000000U}, /* 3 (ADC_AE_1_0) */ \
98+
{0x00001FFFU, 0x00000000U}, /* 4 (ADC_AE_1_1) */ \
99+
{0x00001FFFU, 0x00000000U}, /* 5 (ADC_AE_2_0) */ \
100+
{0x00001FFFU, 0x00000000U}, /* 6 (ADC_AE_2_1) */ \
101+
}
102+
/* Adc Channels are divided into 2 Groups. */
103+
/* This array shows max number of channels of each group. */
104+
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
105+
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
106+
#define ADC_SAR_IP_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
107+
{8U, 8U}, /* 1 */ \
108+
{24U, 0U}, /* 2 (ADC_AE_0_0) */ \
109+
{13U, 0U}, /* 3 (ADC_AE_1_0) */ \
110+
{13U, 0U}, /* 4 (ADC_AE_1_1) */ \
111+
{13U, 0U}, /* 5 (ADC_AE_2_0) */ \
112+
{13U, 0U}, /* 6 (ADC_AE_2_1) */ \
113+
}
114+
/* Number of group channels of each unit */
115+
/* Unit 0 / 1 / 2 (ADC_AE_0_0)/ 3 (ADC_AE_1_0)/ 4 (ADC_AE_1_1)/ 5 (ADC_AE_2_0)/ 6 (ADC_AE_2_1) */
116+
#define ADC_SAR_IP_MAX_GROUP_COUNT { 2U, 2U, 1U, 1U, 1U, 1U, 1U }
117+
/* Bit0: DSDR is available
118+
Bit1: PSCR is available
119+
Bit2: CTU is available
120+
Bit3: CTU trigger mode is available */
121+
#define ADC_SAR_IP_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
122+
0x0000000EU, /* 1 */ \
123+
0x00000002U, /* 2 (ADC_AE_0_0) */ \
124+
0x0000000EU, /* 3 (ADC_AE_1_0) */ \
125+
0x0000000EU, /* 4 (ADC_AE_1_1) */ \
126+
0x0000000EU, /* 5 (ADC_AE_2_0) */ \
127+
0x0000000EU, /* 6 (ADC_AE_2_1) */ \
101128
}
102-
/* Adc Channels are divided into 2 Groups. */
103-
/* This array shows max number of channels of each group. */
104-
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
105-
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
106-
#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \
107-
{8U, 8U}, /* 1 */ \
108-
{24U, 0U}, /* 2 (ADC_AE_0_0) */ \
109-
{13U, 0U}, /* 3 (ADC_AE_1_0) */ \
110-
{13U, 0U}, /* 4 (ADC_AE_1_1) */ \
111-
{13U, 0U}, /* 5 (ADC_AE_2_0) */ \
112-
{13U, 0U}, /* 6 (ADC_AE_2_1) */ \
113-
}
114-
/* Number of group channels of each unit */
115-
/* Unit 0 / 1 / 2 (ADC_AE_0_0)/ 3 (ADC_AE_1_0)/ 4 (ADC_AE_1_1)/ 5 (ADC_AE_2_0)/ 6 (ADC_AE_2_1) */
116-
#define FEATURE_ADC_MAX_GROUP_COUNT { 2U, 2U, 1U, 1U, 1U, 1U, 1U }
117-
/* Bit0: DSDR is available
118-
Bit1: PSCR is available
119-
Bit2: CTU is available
120-
Bit3: CTU trigger mode is available */
121-
#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \
122-
0x0000000EU, /* 1 */ \
123-
0x00000002U, /* 2 (ADC_AE_0_0) */ \
124-
0x00000006U, /* 3 (ADC_AE_1_0) */ \
125-
0x00000006U, /* 4 (ADC_AE_1_1) */ \
126-
0x00000006U, /* 5 (ADC_AE_2_0) */ \
127-
0x00000006U, /* 6 (ADC_AE_2_1) */ \
128-
}
129129

130130
/* Register access defines */
131131
#define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)]))))

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