Skip to content

hal_nxp: Sync MCXA344 header files in 25.09.00 to hal_nxp #608

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 1 commit into from
Closed

hal_nxp: Sync MCXA344 header files in 25.09.00 to hal_nxp #608

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
242 changes: 242 additions & 0 deletions dts/nxp/mcx/MCXA344VFM-pinctrl.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,242 @@
/*
* NOTE: Autogenerated file by gen_soc_headers.py
* for MCXA344VFM/signal_configuration.xml
*
*
*/

#ifndef _ZEPHYR_DTS_BINDING_MCXA344VFM_
#define _ZEPHYR_DTS_BINDING_MCXA344VFM_

#define A15X_MUX(port, pin, mux) \
(((((port) - '0') & 0xF) << 28) | \
(((pin) & 0x3F) << 22) | \
(((mux) & 0xF) << 8))

#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */
#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */
#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */
#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */
#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */
#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */
#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */
#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */
#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */
#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */
#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */
#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */
#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */
#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */
#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */
#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */
#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */
#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */
#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */
#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */
#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */
#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */
#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */
#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */
#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */
#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */
#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */
#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */
#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */
#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */
#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */
#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */
#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */
#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */
#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */
#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */
#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */
#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */
#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
#define CMP2_IN3_P1_2 A15X_MUX('1',2,0) /* PT1_2 */
#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */
#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */
#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */
#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */
#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */
#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */
#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */
#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */
#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */
#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */
#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */
#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */
#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */
#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */
#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */
#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */
#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */
#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */
#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */
#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */
#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */
#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */
#define SMARTDMA_PIO4_P1_8 A15X_MUX('1',8,7) /* PT1_8 */
#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */
#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */
#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */
#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */
#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */
#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */
#define SMARTDMA_PIO5_P1_9 A15X_MUX('1',9,7) /* PT1_9 */
#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */
#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */
#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */
#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */
#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */
#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */
#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */
#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */
#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */
#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */
#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */
#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */
#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */
#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */
#define CMP2_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
#define CMP1_INN4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */
#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */
#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */
#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */
#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */
#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */
#define SMARTDMA_PIO26_P2_2 A15X_MUX('2',2,7) /* PT2_2 */
#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */
#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
#define ADC0_A3_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */
#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */
#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */
#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */
#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */
#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */
#define SMARTDMA_PIO27_P2_3 A15X_MUX('2',3,7) /* PT2_3 */
#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */
#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */
#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */
#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */
#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */
#define SMARTDMA_PIO31_P2_7 A15X_MUX('2',7,7) /* PT2_7 */
#define OPAMP0_INP_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */
#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */
#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */
#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */
#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */
#define SMARTDMA_PIO16_P2_12 A15X_MUX('2',12,7) /* PT2_12 */
#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */
#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */
#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */
#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */
#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */
#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */
#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */
#define SMARTDMA_PIO17_P2_13 A15X_MUX('2',13,7) /* PT2_13 */
#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */
#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
#define WUU0_IN21_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
#define CMP0_INP4_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */
#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */
#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */
#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */
#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */
#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */
#define SMARTDMA_PIO18_P2_15 A15X_MUX('2',15,7) /* PT2_15 */
#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */
#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */
#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */
#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */
#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */
#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */
#define SMARTDMA_PIO20_P2_17 A15X_MUX('2',17,7) /* PT2_17 */
#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */
#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */
#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */
#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */
#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */
#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */
#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */
#define SMARTDMA_PIO0_P3_0 A15X_MUX('3',0,10) /* PT3_0 */
#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */
#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */
#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */
#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */
#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */
#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */
#define SMARTDMA_PIO1_P3_1 A15X_MUX('3',1,10) /* PT3_1 */
#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */
#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */
#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */
#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */
#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */
#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */
#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */
#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */
#define SMARTDMA_PIO8_P3_8 A15X_MUX('3',8,10) /* PT3_8 */
#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */
#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */
#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */
#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */
#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */
#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */
#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */
#define SMARTDMA_PIO9_P3_9 A15X_MUX('3',9,10) /* PT3_9 */
#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */
#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */
#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */
#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */
#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */
#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */
#define SMARTDMA_PIO10_P3_10 A15X_MUX('3',10,10) /* PT3_10 */
#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */
#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */
#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */
#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */
#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */
#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */
#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */
#define SMARTDMA_PIO11_P3_11 A15X_MUX('3',11,10) /* PT3_11 */
#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */
#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */
#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */
#define LPI2C1_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */
#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */
#define PWM1_A3_P3_27 A15X_MUX('3',27,7) /* PT3_27 */
#define SMARTDMA_PIO27_P3_27 A15X_MUX('3',27,10) /* PT3_27 */
#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */
#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */
#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */
#define LPI2C1_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */
#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */
#define PWM1_B3_P3_28 A15X_MUX('3',28,7) /* PT3_28 */
#define SMARTDMA_PIO28_P3_28 A15X_MUX('3',28,10) /* PT3_28 */
#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */
#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */
#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */
#define LPI2C1_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */
#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */
#define SMARTDMA_PIO29_P3_29 A15X_MUX('3',29,10) /* PT3_29 */
#endif
Loading