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duynguyenxaKhiemNguyenT
duynguyenxa
authored and
KhiemNguyenT
committed
hal: ra: Fix pll clock config get from dts
The new update of dts in device tree make pll source clock choose have issue. We update macro to get the div and freq of pll p q r by using inforamtion in pll out line Signed-off-by: Duy Nguyen <[email protected]>
1 parent 6ebe2c4 commit 02b399d

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-36
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3 files changed

+36
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‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/bsp_clock_cfg.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,12 @@
4040
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
4141
#endif
4242

43-
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
44-
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
45-
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
46-
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
47-
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
48-
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
43+
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
44+
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
45+
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
46+
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
47+
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
48+
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))
4949

5050
#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
5151
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
@@ -58,12 +58,12 @@
5858
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
5959
#endif
6060

61-
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
62-
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
63-
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
64-
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
65-
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
66-
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
61+
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
62+
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
63+
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
64+
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
65+
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
66+
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))
6767

6868
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
6969
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_clock_cfg.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,12 @@
4040
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
4141
#endif
4242

43-
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
44-
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
45-
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
46-
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
47-
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
48-
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
43+
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
44+
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
45+
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
46+
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
47+
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
48+
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))
4949

5050
#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
5151
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
@@ -58,12 +58,12 @@
5858
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
5959
#endif
6060

61-
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
62-
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
63-
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
64-
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
65-
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
66-
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
61+
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
62+
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
63+
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
64+
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
65+
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
66+
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))
6767

6868
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
6969
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/bsp_clock_cfg.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -39,12 +39,12 @@
3939
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
4040
#endif
4141

42-
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll), divp, 2)
43-
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0))
44-
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll), divq, 2)
45-
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0))
46-
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll), divr, 2)
47-
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0))
42+
#define BSP_CFG_PLODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pllp), div, 2)
43+
#define BSP_CFG_PLL1P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllp), freq, 0))
44+
#define BSP_CFG_PLODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pllq), div, 2)
45+
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllq), freq, 0))
46+
#define BSP_CFG_PLODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pllr), div, 2)
47+
#define BSP_CFG_PLL1R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pllr), freq, 0))
4848

4949
#define BSP_CFG_PLL2_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll2)))
5050
#define BSP_CFG_PLL2_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll2), div, 1)
@@ -57,12 +57,12 @@
5757
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
5858
#endif
5959

60-
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divp, 2)
61-
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0))
62-
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divq, 2)
63-
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0))
64-
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2), divr, 2)
65-
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0))
60+
#define BSP_CFG_PL2ODIVP RA_CGC_CLK_DIV(DT_NODELABEL(pll2p), div, 2)
61+
#define BSP_CFG_PLL2P_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2p), freq, 0))
62+
#define BSP_CFG_PL2ODIVQ RA_CGC_CLK_DIV(DT_NODELABEL(pll2q), div, 2)
63+
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2q), freq, 0))
64+
#define BSP_CFG_PL2ODIVR RA_CGC_CLK_DIV(DT_NODELABEL(pll2r), div, 2)
65+
#define BSP_CFG_PLL2R_FREQUENCY_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2r), freq, 0))
6666

6767
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
6868
#define BSP_CFG_CPUCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cpuclk), div, 1)

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