|
| 1 | +/* |
| 2 | +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates |
| 3 | +* |
| 4 | +* SPDX-License-Identifier: BSD-3-Clause |
| 5 | +*/ |
| 6 | + |
| 7 | +#ifndef R_MIPI_PHY_H |
| 8 | +#define R_MIPI_PHY_H |
| 9 | + |
| 10 | +/*********************************************************************************************************************** |
| 11 | + * Includes |
| 12 | + **********************************************************************************************************************/ |
| 13 | + |
| 14 | +#include "bsp_api.h" |
| 15 | + |
| 16 | +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ |
| 17 | +FSP_HEADER |
| 18 | + |
| 19 | +/*******************************************************************************************************************//** |
| 20 | + * @addtogroup MIPI_PHY |
| 21 | + * @{ |
| 22 | + **********************************************************************************************************************/ |
| 23 | + |
| 24 | +/*********************************************************************************************************************** |
| 25 | + * Macro definitions |
| 26 | + **********************************************************************************************************************/ |
| 27 | + |
| 28 | +/*********************************************************************************************************************** |
| 29 | + * Typedef definitions |
| 30 | + **********************************************************************************************************************/ |
| 31 | + |
| 32 | +/* MIPI_PHY PLL speed configuration */ |
| 33 | +typedef union |
| 34 | +{ |
| 35 | + __PACKED_STRUCT |
| 36 | + { |
| 37 | + uint8_t div; ///< PHY PLL divisor |
| 38 | + uint8_t mul_frac; ///< PHY PLL fractional multiplier (0, 1/3, 2/3, or 1/2) |
| 39 | + uint16_t mul_int; ///< PHY PLL integer multiplier (1-based) |
| 40 | + }; |
| 41 | + uint32_t raw; |
| 42 | +} mipi_phy_pll_cfg_t; |
| 43 | + |
| 44 | +/** MIPI PHY D-PHY power mode transition timing */ |
| 45 | +typedef struct st_mipi_phy_timing |
| 46 | +{ |
| 47 | + uint32_t t_init : 19; ///< Minimum duration of the TINIT state (Units: PCLKA cycles) |
| 48 | + uint32_t : 13; // Padding |
| 49 | + uint8_t t_clk_prep; ///< Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state) |
| 50 | + uint8_t t_hs_prep; ///< Duration of the data lane LP-00 state (immediately before entry to the HS-0 state) |
| 51 | + union |
| 52 | + { |
| 53 | + __PACKED_STRUCT |
| 54 | + { |
| 55 | + uint8_t t_clk_zero; ///< TCLKZERO setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information |
| 56 | + uint8_t t_clk_pre; ///< TCLKPRE setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information |
| 57 | + uint8_t t_clk_post; ///< TCLKPOST setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information |
| 58 | + uint8_t t_clk_trail; ///< TCLKTRAIL setting. See Figure 57.1 in User Manual (R01UH0995EJ0060) for more information |
| 59 | + } dphytim4_b; |
| 60 | + uint32_t dphytim4; ///< Clock lane pre and post data timing settings |
| 61 | + }; |
| 62 | + union |
| 63 | + { |
| 64 | + __PACKED_STRUCT |
| 65 | + { |
| 66 | + uint8_t t_hs_zero; ///< THSZERO setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information |
| 67 | + uint8_t t_hs_trail; ///< THSTRAIL setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information |
| 68 | + uint8_t t_hs_exit; ///< THSEXIT setting. See Figure 57.1 in User Maual (R01UH0995EJ0060) for more information |
| 69 | + uint8_t : 8; |
| 70 | + } dphytim5_b; |
| 71 | + uint32_t dphytim5; ///< High-Speed data lane timing settings |
| 72 | + }; |
| 73 | + uint8_t t_lp_exit; ///< Low-power transition time to High-Speed mode |
| 74 | +} mipi_phy_timing_t; |
| 75 | + |
| 76 | +/** MIPI_PHY configuration structure. */ |
| 77 | +typedef struct st_mipi_phy_cfg |
| 78 | +{ |
| 79 | + mipi_phy_pll_cfg_t pll_settings; ///< PHY PLL configuration (DPHYPLFCR) |
| 80 | + uint8_t lp_divisor : 5; ///< PHY PLL LP speed divisor setting (DPHYESCCR) |
| 81 | + mipi_phy_timing_t const * p_timing; ///< Pointer to D-PHY HS/LP transition timing values |
| 82 | +} mipi_phy_cfg_t; |
| 83 | + |
| 84 | +/** MIPI_PHY instance control block. */ |
| 85 | +typedef struct st_mipi_phy_ctrl |
| 86 | +{ |
| 87 | + uint32_t open; |
| 88 | + mipi_phy_cfg_t const * p_cfg; |
| 89 | +} mipi_phy_ctrl_t; |
| 90 | + |
| 91 | +/** Private Interface definition for MIPI PHY peripheral */ |
| 92 | +typedef struct st_mipi_phy_api |
| 93 | +{ |
| 94 | + /** Open MIPI PHY device. |
| 95 | + * @param[in,out] p_ctrl Pointer to MIPI PHY interface control block. |
| 96 | + * @param[in] p_cfg Pointer to MIPI PHY configuration structure. |
| 97 | + */ |
| 98 | + fsp_err_t (* open)(mipi_phy_ctrl_t * const p_ctrl, mipi_phy_cfg_t const * const p_cfg); |
| 99 | + |
| 100 | + /** Close MIPI PHY device. |
| 101 | + * @param[in] p_ctrl Pointer to MIPI PHY interface control block. |
| 102 | + */ |
| 103 | + fsp_err_t (* close)(mipi_phy_ctrl_t * const p_ctrl); |
| 104 | +} mipi_phy_api_t; |
| 105 | + |
| 106 | +/** This structure encompasses everything that is needed to use an instance of this interface. */ |
| 107 | +typedef struct st_mipi_phy_instance |
| 108 | +{ |
| 109 | + mipi_phy_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance |
| 110 | + mipi_phy_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance |
| 111 | + mipi_phy_api_t const * p_api; ///< Pointer to the API structure for this instance |
| 112 | +} mipi_phy_instance_t; |
| 113 | + |
| 114 | +/********************************************************************************************************************** |
| 115 | + * Exported global variables |
| 116 | + **********************************************************************************************************************/ |
| 117 | + |
| 118 | +/** @cond INC_HEADER_DEFS_SEC */ |
| 119 | +/** Filled in Interface API structure for this Instance. */ |
| 120 | +extern const mipi_phy_api_t g_mipi_phy; |
| 121 | + |
| 122 | +/** @endcond */ |
| 123 | + |
| 124 | +/*********************************************************************************************************************** |
| 125 | + * Exported global functions (to be accessed by other files) |
| 126 | + **********************************************************************************************************************/ |
| 127 | + |
| 128 | +/*********************************************************************************************************************** |
| 129 | + * Instance Functions (Note: This is not a public API and should not be called directly) |
| 130 | + **********************************************************************************************************************/ |
| 131 | +fsp_err_t r_mipi_phy_open(mipi_phy_ctrl_t * const p_api_ctrl, mipi_phy_cfg_t const * const p_cfg); |
| 132 | +fsp_err_t r_mipi_phy_close(mipi_phy_ctrl_t * const p_api_ctrl); |
| 133 | + |
| 134 | +/*******************************************************************************************************************//** |
| 135 | + * @} (end defgroup MIPI_PHY) |
| 136 | + **********************************************************************************************************************/ |
| 137 | + |
| 138 | +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ |
| 139 | +FSP_FOOTER |
| 140 | + |
| 141 | +#endif // R_MIPI_PHY_H |
0 commit comments