hal: renesas: ra: Fix mistakes in header files

bsp_feature_gen.h: Add lacking information when migrate to FSPv5.3.0
*_cfg.h: Correct mistakes
CMakeLists.txt: Remove redundant code and add empty line at the end

Signed-off-by: Thao Luong <[email protected]>

Author: thaoluonguw

ra/CMakeLists.txt

@@ -19,12 +19,11 @@ set(srcs
 zephyr_include_directories(${include_dirs})
 zephyr_library_sources(${srcs})
 
-message(${CONFIG_SOC_SERIES})
 zephyr_include_directories(fsp/ra/fsp/src/bsp/mcu/${CONFIG_SOC_SERIES})
 zephyr_include_directories(ra_cfg/fsp_cfg/bsp/${CONFIG_SOC_SERIES})
 
 # Optional build base on feature configuration
 zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SCI_B_UART
 	fsp/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c)
 zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_DTC
-	fsp/ra/fsp/src/r_dtc/r_dtc.c)
+	fsp/ra/fsp/src/r_dtc/r_dtc.c)

ra/fsp/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature_gen.h

@@ -26,5 +26,15 @@
 /***********************************************************************************************************************
  * Private global variables and functions
  **********************************************************************************************************************/
+
+// *UNCRUSTIFY-OFF*
+#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK  (0xFF)
+#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED     (0x1)
+#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK             (0)
+#define BSP_FEATURE_GPT_GPTE_SUPPORTED                (0)
+#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK            (0)
+#define BSP_FEATURE_GPT_GPTEH_SUPPORTED               (0)
+#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK              (0x1)
+#define BSP_FEATURE_GPT_OPS_SUPPORTED                 (0x1)
 // *UNCRUSTIFY-ON*
 #endif

ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_cfg.h

@@ -1,16 +1,15 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_
-#define ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
 
 #include "soc.h"
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
-
 #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
 
 /* Add for zephyr porting */
@@ -33,4 +32,4 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_ */
+#endif /* BSP_CFG_H_ */

ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_clock_cfg.h

@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
+* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
 
 #include <zephyr/devicetree.h>
 

ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_device_cfg.h

@@ -1,9 +1,8 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
+* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
 #ifndef BSP_MCU_DEVICE_CFG_H_
 #define BSP_MCU_DEVICE_CFG_H_
 #define BSP_CFG_MCU_PART_SERIES (8)

ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_device_pn_cfg.h

@@ -1,19 +1,15 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
+* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
 #ifndef BSP_MCU_DEVICE_PN_CFG_H_
-
-#if defined(CONFIG_SOC_R7FA8M1AHECBD)
+#define BSP_MCU_DEVICE_PN_CFG_H_
 #define BSP_MCU_R7FA8M1AHECBD
-#define BSP_MCU_FEATURE_SET       ('A')
-#define BSP_ROM_SIZE_BYTES        (2064384)
-#define BSP_RAM_SIZE_BYTES        (917504)
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (2064384)
+#define BSP_RAM_SIZE_BYTES (917504)
 #define BSP_DATA_FLASH_SIZE_BYTES (12288)
 #define BSP_PACKAGE_BGA
 #define BSP_PACKAGE_PINS (224)
-#endif
-
 #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */