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hal: renesas: rz: Initial support for PINCTRL and GPIO for RZ/A
Initial HAL support for PINCTRL and GPIO of RZ/A Signed-off-by: Phuc Pham <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/fsp/inc/instances/rza/r_ioport.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @addtogroup IOPORT
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* @{
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**********************************************************************************************************************/
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#ifndef R_IOPORT_H
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#define R_IOPORT_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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#include "r_ioport_api.h"
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#if __has_include("r_ioport_cfg.h")
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#include "r_ioport_cfg.h"
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#endif
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/* Private definition to set enumeration values. */
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#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
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typedef struct st_ioport_instance_ctrl
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{
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uint32_t open;
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void const * p_context;
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ioport_cfg_t const * p_cfg;
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} ioport_instance_ctrl_t;
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#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T
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/** Superset of all peripheral functions. */
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typedef enum e_ioport_peripheral
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{
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/** Pin will function as a Mode0 peripheral pin */
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IOPORT_PERIPHERAL_MODE0 = (0x0UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode1 peripheral pin */
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IOPORT_PERIPHERAL_MODE1 = (0x1UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode2 peripheral pin */
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IOPORT_PERIPHERAL_MODE2 = (0x2UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode3 peripheral pin */
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IOPORT_PERIPHERAL_MODE3 = (0x3UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode4 peripheral pin */
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IOPORT_PERIPHERAL_MODE4 = (0x4UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode5 peripheral pin */
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IOPORT_PERIPHERAL_MODE5 = (0x5UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode6 peripheral pin */
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IOPORT_PERIPHERAL_MODE6 = (0x6UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode7 peripheral pin */
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IOPORT_PERIPHERAL_MODE7 = (0x7UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode8 peripheral pin */
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IOPORT_PERIPHERAL_MODE8 = (0x8UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode9 peripheral pin */
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IOPORT_PERIPHERAL_MODE9 = (0x9UL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode10 peripheral pin */
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IOPORT_PERIPHERAL_MODE10 = (0xAUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode11 peripheral pin */
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IOPORT_PERIPHERAL_MODE11 = (0xBUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode12 peripheral pin */
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IOPORT_PERIPHERAL_MODE12 = (0xCUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode13 peripheral pin */
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IOPORT_PERIPHERAL_MODE13 = (0xDUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode14 peripheral pin */
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IOPORT_PERIPHERAL_MODE14 = (0xEUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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/** Pin will function as a Mode15 peripheral pin */
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IOPORT_PERIPHERAL_MODE15 = (0xFUL << IOPORT_PRV_PFS_PSEL_OFFSET),
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} ioport_peripheral_t;
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#endif
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#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T
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/** Options to configure pin functions */
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typedef enum e_ioport_cfg_options
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{
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/* For PM Register */
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IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000, ///< Sets the pin direction to Hi-Z (default)
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IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000004, ///< Sets the pin direction to input
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IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000008, ///< Sets the pin direction to output (input disable)
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IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x0000000C, ///< Sets the pin direction to output (input enable)
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/* For P Register */
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IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
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IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
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/* For PUPD Register */
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IOPORT_CFG_PULLUP_PULLDOWN_DISABLE = 0x00000000, ///< Disable the pin's internal pull-up and pull-down
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IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
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IOPORT_CFG_PULLDOWN_ENABLE = 0x00000020, ///< Enables the pin's internal pull-down
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/* For NOD Register */
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IOPORT_CFG_NOD_DISABLE = 0x00000000, ///< Disable the pin's N-ch open-drain
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IOPORT_CFG_NOD_ENABLE = 0x00000040, ///< Enables the pin's N-ch open-drain
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/* For SMT Register */
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IOPORT_CFG_SCHMITT_DISABLE = 0x00000000, ///< Disable the pin's Schmitt-trigger input
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IOPORT_CFG_SCHMITT_ENABLE = 0x80000000, ///< Enables the pin's Schmitt-trigger input
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/* For IOLH Register */
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IOPORT_CFG_DRIVE_B00 = 0x00000000, ///< Sets the IOLH register value to b'00
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IOPORT_CFG_DRIVE_B01 = 0x00000400, ///< Sets the IOLH register value to b'01
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IOPORT_CFG_DRIVE_B10 = 0x00000800, ///< Sets the IOLH register value to b'10
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IOPORT_CFG_DRIVE_B11 = 0x00000C00, ///< Sets the IOLH register value to b'11
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/* For ISEL Register */
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IOPORT_CFG_TINT_DISABLE = 0x00000000, ///< Disable IRQ functionality for a pin
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IOPORT_CFG_TINT_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
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/* For SR Register */
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IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000, ///< Sets the pin slew-rate to slow
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IOPORT_CFG_SLEW_RATE_FAST = 0x00020000, ///< Sets the pin slew-rate to fast
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/* For IEN Register */
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IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_DISABLE = 0x00000000, ///< Disable input the pin of special purpose port
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IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_ENABLE = 0x00040000, ///< Sets the pin of special purpose port to input
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/* For FILONOFF Register */
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IOPORT_CFG_NOISE_FILTER_OFF = 0x00000000, ///< Noise filter disable
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IOPORT_CFG_NOISE_FILTER_ON = 0x00080000, ///< Noise filter enable
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/* For FILNUM Register */
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IOPORT_CFG_NOISE_FILTER_NUM_4STAGE = 0x00000000, ///< Sets the pin noise filter to 4-stage filter
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IOPORT_CFG_NOISE_FILTER_NUM_8STAGE = 0x00100000, ///< Sets the pin noise filter to 8-stage filter
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IOPORT_CFG_NOISE_FILTER_NUM_12STAGE = 0x00200000, ///< Sets the pin noise filter to 12-stage filter
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IOPORT_CFG_NOISE_FILTER_NUM_16STAGE = 0x00300000, ///< Sets the pin noise filter to 16-stage filter
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/* For FILCLKSEL Register */
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IOPORT_CFG_NOISE_FILTER_DIVIDED_B00 = 0x00000000, ///< Sets the FILCLKSEL register value to b'00
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IOPORT_CFG_NOISE_FILTER_DIVIDED_B01 = 0x00400000, ///< Sets the FILCLKSEL register value to b'01
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IOPORT_CFG_NOISE_FILTER_DIVIDED_B10 = 0x00800000, ///< Sets the FILCLKSEL register value to b'10
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IOPORT_CFG_NOISE_FILTER_DIVIDED_B11 = 0x00C00000, ///< Sets the FILCLKSEL register value to b'11
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/* For PMC Register */
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IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
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} ioport_cfg_options_t;
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#endif
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/** Pin selection for port group
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_pin_selection
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{
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IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group
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IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group
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IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group
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} ioport_event_pin_selection_t;
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/** Port group operation
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_output_operation
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{
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IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation
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IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation
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IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation
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IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation
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} ioport_event_output_operation_t;
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/** Input port group event control
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_control
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{
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IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link
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IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link
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} ioport_event_control_t;
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/** Single port event direction
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_direction
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{
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IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port
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IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port
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} ioport_event_direction_t;
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/** Input event edge detection
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_detection
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{
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IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event
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IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event
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IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event
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} ioport_event_detection_t;
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/** Initial value for buffer register
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* @note Event link must be configured by the ELC
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*/
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typedef enum e_ioport_event_initial_buffer_value
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{
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IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low to initial value of buffer register for input port group
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IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high to initial value of buffer register for input port group
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} ioport_event_initial_buffer_value_t;
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/** Single port configuration
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* @note Event link must be configured by the ELC
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*/
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typedef struct st_ioport_event_single
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{
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ioport_event_control_t event_control; ///< Event link control for single port
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ioport_event_direction_t direction; ///< Event direction for single port
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uint16_t port_num; ///< Port number specified to single port
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ioport_event_output_operation_t operation; ///< Single port operation select
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ioport_event_detection_t edge_detection; ///< Edge detection select
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} ioport_event_single_t;
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/** Output port group configuration
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* @note Event link must be configured by the ELC
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*/
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typedef struct st_ioport_event_group_output
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{
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uint8_t pin_select; ///< Port number specified to output port group
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ioport_event_output_operation_t operation; ///< Port group operation select
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} ioport_event_group_output_t;
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/** Input port group configuration
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* @note Event link must be configured by the ELC
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*/
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typedef struct st_ioport_event_group_input
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{
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ioport_event_control_t event_control; ///< Event link control for input port group
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ioport_event_detection_t edge_detection; ///< Edge detection select
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ioport_event_control_t overwrite_control; ///< Buffer register overwrite control
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uint8_t pin_select; ///< Port number specified to input port group
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uint8_t buffer_init_value; ///< Buffer register initial value
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} ioport_event_group_input_t;
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/** IOPORT extended configuration for event link function
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* @note Event link must be configured by the ELC
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*/
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typedef struct st_ioport_extend_cfg
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{
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ioport_event_group_output_t const * p_port_group_output_cfg; ///< Pointer to output port group configuration
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ioport_event_group_input_t const * p_port_group_input_cfg; ///< Pointer to input port group configuration
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ioport_event_single_t const * p_single_port_cfg; ///< Pointer to single input port configuration
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} ioport_extend_cfg_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const ioport_api_t g_ioport_on_ioport;
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/** @endcond */
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/***********************************************************************************************************************
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* Public APIs
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**********************************************************************************************************************/
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fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
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fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
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fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
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fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
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fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
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fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
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fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
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fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
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fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
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bsp_io_port_t port,
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ioport_size_t direction_values,
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ioport_size_t mask);
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fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
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fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
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bsp_io_port_t port,
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ioport_size_t event_data,
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ioport_size_t mask_value);
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fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
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fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
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/*******************************************************************************************************************//**
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* @} (end defgroup IOPORT)
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif // R_IOPORT_H

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