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stm32cube: update stm32h7rs to cube version V1.2.0
Update Cube version for STM32H7RSxx series on https://github.com/STMicroelectronics from version v1.1.0 to version v1.2.0 Signed-off-by: Fabrice DJIATSA <[email protected]>
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‎stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h‎

Lines changed: 79 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,7 @@ extern "C" {
139139
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
140140
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
141141
#if defined(STM32L0)
142+
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
142143
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
143144
input 1 for COMP1, LPTIM input 2 for COMP2 */
144145
#endif
@@ -241,8 +242,10 @@ extern "C" {
241242
*/
242243
#if defined(STM32H5) || defined(STM32C0)
243244
#else
245+
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
244246
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
245247
inter STM32 series compatibility */
248+
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
246249
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
247250
inter STM32 series compatibility */
248251
#endif
@@ -473,7 +476,7 @@ extern "C" {
473476
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474477
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475478
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
476-
#define PAGESIZE FLASH_PAGE_SIZE
479+
/* #define PAGESIZE FLASH_PAGE_SIZE */
477480
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
478481
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
479482
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
@@ -542,6 +545,10 @@ extern "C" {
542545
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543546
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544547
#endif /* STM32H7RS */
548+
#if defined(STM32H7RS)
549+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
550+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
551+
#endif /* STM32H7RS */
545552
#if defined(STM32U5)
546553
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
547554
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -606,6 +613,15 @@ extern "C" {
606613

607614
#endif /* STM32U5 */
608615

616+
#if defined(STM32U5)
617+
618+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
619+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
620+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
621+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
622+
623+
#endif /* STM32U5 */
624+
609625
#if defined(STM32H5)
610626
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
611627
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -884,6 +900,10 @@ extern "C" {
884900
#define HRTIMInterruptResquests HRTIMInterruptRequests
885901
#endif /* STM32F3 || STM32G4 || STM32H7 */
886902

903+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
904+
#define HRTIMInterruptResquests HRTIMInterruptRequests
905+
#endif /* STM32F3 || STM32G4 || STM32H7 */
906+
887907
#if defined(STM32G4)
888908
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
889909
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -1023,6 +1043,7 @@ extern "C" {
10231043
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
10241044
#endif /* STM32F3 */
10251045

1046+
10261047
/**
10271048
* @}
10281049
*/
@@ -1273,10 +1294,12 @@ extern "C" {
12731294
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12741295
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12751296

1297+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12761298
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12771299
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12781300
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
12791301
#endif /* STM32H5 || STM32H7RS || STM32N6 */
1302+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12801303

12811304
#if defined(STM32WBA)
12821305
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1288,27 +1311,33 @@ extern "C" {
12881311
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12891312
#endif /* STM32WBA */
12901313

1314+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12911315
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12921316
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12931317
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
12941318
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
1319+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
12951320

1321+
#if defined(STM32F7) || defined(STM32WB)
12961322
#if defined(STM32F7) || defined(STM32WB)
12971323
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
12981324
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
12991325
#endif /* STM32F7 || STM32WB */
1326+
#endif /* STM32F7 || STM32WB */
13001327

13011328
#if defined(STM32H7)
13021329
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
13031330
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
13041331
#endif /* STM32H7 */
13051332

1333+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13061334
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13071335
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
13081336
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
13091337
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
13101338
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
13111339
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
1340+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
13121341

13131342
/**
13141343
* @}
@@ -1475,6 +1504,7 @@ extern "C" {
14751504
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14761505
#endif
14771506

1507+
#if defined(STM32U5) || defined(STM32MP2)
14781508
#if defined(STM32U5) || defined(STM32MP2)
14791509
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14801510
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
@@ -1592,34 +1622,43 @@ extern "C" {
15921622
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
15931623
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
15941624
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
1625+
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
15951626
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
15961627
the MAC transmitter) */
1628+
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
15971629
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
15981630
MAC transmitter */
15991631
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
16001632
or flushing the TxFIFO */
16011633
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
16021634
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
1635+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
16031636
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
16041637
of previous frame or IFG/backoff period to be over */
1638+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
16051639
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
16061640
transmitting a Pause control frame (in full duplex mode) */
1641+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
16071642
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
16081643
frame for transmission */
16091644
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
16101645
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
1646+
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
16111647
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
16121648
de-activate threshold */
1649+
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
16131650
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
16141651
activate threshold */
16151652
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
16161653
#if defined(STM32F1)
16171654
#else
16181655
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
16191656
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
1657+
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
16201658
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
16211659
(or time-stamp) */
16221660
#endif
1661+
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
16231662
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
16241663
status */
16251664
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
@@ -2024,11 +2063,13 @@ extern "C" {
20242063
* @{
20252064
*/
20262065
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
2066+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20272067
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20282068
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20292069
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20302070
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
20312071
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
2072+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20322073

20332074
/**
20342075
* @}
@@ -2490,8 +2531,10 @@ extern "C" {
24902531
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
24912532
* @{
24922533
*/
2534+
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
24932535
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
24942536
done into HAL_COMP_Init() */
2537+
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
24952538
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
24962539
done into HAL_COMP_Init() */
24972540
/**
@@ -3688,9 +3731,15 @@ extern "C" {
36883731
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
36893732
#endif
36903733

3734+
#if defined(STM32U0)
3735+
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3736+
#endif
3737+
36913738
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
36923739
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
36933740
defined(STM32U0)
3741+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3742+
defined(STM32U0)
36943743
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36953744
#else
36963745
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3943,6 +3992,8 @@ extern "C" {
39433992
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
39443993
defined (STM32WBA) || defined (STM32H5) || \
39453994
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
3995+
defined (STM32WBA) || defined (STM32H5) || \
3996+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39463997
#else
39473998
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39483999
#endif
@@ -4263,6 +4314,33 @@ extern "C" {
42634314
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
42644315
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
42654316
#endif
4317+
#if defined(STM32U5)
4318+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4319+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4320+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4321+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4322+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4323+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4324+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4325+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4326+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4327+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4328+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4329+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4330+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4331+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4332+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4333+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4334+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4335+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4336+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4337+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4338+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4339+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4340+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4341+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4342+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
4343+
#endif
42664344
/**
42674345
* @}
42684346
*/

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