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This PR adds STM32CubeN6 1.0.0

Add version 1.0.0 of STM32CubeN6

Signed-off-by: Guillaume Gautier <[email protected]>
Regenerates LL headers to add the STM32N6.

Signed-off-by: Guillaume Gautier <[email protected]>
Remove legacy macro PAGESIZE which conflicts with POSIX.

Signed-off-by: Guillaume Gautier <[email protected]>
To use FSBL mode, add the following fix:
-Remove CMSE_NS_ENTRY modifier, which requires enabling
CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS

Signed-off-by: Guillaume Gautier <[email protected]>
Add STM32N6 to the list of supported series and add the compile definition
for compiling on a Cortex M55

Signed-off-by: Guillaume Gautier <[email protected]>
Adds STM32N6 to the pinctrl generation script.

Signed-off-by: Guillaume Gautier <[email protected]>
Fixes the regex used to generate XSPIM pins:
* NCS pins are numbered 1-2 instead of 0-1
* Expand IO numbers beyond 7 (necessary for STM32N6)

Signed-off-by: Guillaume Gautier <[email protected]>
Adds STM32N6 pinctrl dtsi files.

Signed-off-by: Guillaume Gautier <[email protected]>
@erwango erwango merged commit 1d1f818 into zephyrproject-rtos:main Jan 24, 2025
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3 participants