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Update RISC-V binutils 2.32
Pull in fixes from https://github.com/riscv/riscv-binutils-gdb/tree/riscv-binutils-2.32 Signed-off-by: Kumar Gala <[email protected]>
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‎patches/binutils/2.32/0001-RISC-V-Compress-3-operand-beq-bne-against-x0.patch‎

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From a81304c38b81dc7f2a88c6afdc9f0c1f1083a90a Mon Sep 17 00:00:00 2001
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From: Jim Wilson <[email protected]>
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Date: Fri, 8 Feb 2019 12:57:12 -0800
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Subject: [PATCH 01/11] RISC-V: Compress 3-operand beq/bne against x0.
5+
6+
This lets us accept an instruction like
7+
beq a2,x0,.Label
8+
and generate a compressed beqz. This will allow some future simplications
9+
to the gcc support, e.g. eliminating some duplicate patterns, and avoiding
10+
adding new duplicate patterns, since currently we have to handle signed
11+
and equality compares against zero specially.
12+
13+
Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils
14+
and gcc. There were no regressions.
15+
16+
gas/
17+
* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
18+
(riscv_ip) <'C'>: Add 'z' support.
19+
opcodes/
20+
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
21+
<bne>: Likewise.
22+
---
23+
gas/config/tc-riscv.c | 6 ++++++
24+
opcodes/riscv-opc.c | 2 ++
25+
2 files changed, 8 insertions(+)
26+
27+
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
28+
index 993161568f..99b007f59f 100644
29+
--- a/gas/config/tc-riscv.c
30+
+++ b/gas/config/tc-riscv.c
31+
@@ -586,6 +586,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
32+
case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
33+
case 'w': break; /* RS1S, constrained to equal RD */
34+
case 'x': break; /* RS2S, constrained to equal RD */
35+
+ case 'z': break; /* RS2S, contrained to be x0 */
36+
case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
37+
case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
38+
case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
39+
@@ -1472,6 +1473,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
40+
|| regno != X_SP)
41+
break;
42+
continue;
43+
+ case 'z': /* RS2, contrained to equal x0. */
44+
+ if (!reg_lookup (&s, RCLASS_GPR, &regno)
45+
+ || regno != 0)
46+
+ break;
47+
+ continue;
48+
case '>':
49+
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
50+
|| imm_expr->X_op != O_constant
51+
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
52+
index 72e6b9d48f..bd652590b5 100644
53+
--- a/opcodes/riscv-opc.c
54+
+++ b/opcodes/riscv-opc.c
55+
@@ -247,6 +247,7 @@ const struct riscv_opcode riscv_opcodes[] =
56+
{"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
57+
{"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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+{"beq", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
60+
{"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
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{"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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{"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
63+
@@ -262,6 +263,7 @@ const struct riscv_opcode riscv_opcodes[] =
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{"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
65+
{"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
66+
{"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
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+{"bne", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
68+
{"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
69+
{"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
70+
{"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
71+
--
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2.20.1
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‎patches/binutils/2.32/0002-RISC-V-Fix-linker-crash-in-section-symbol-check.patch‎

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From 535c4d2a313e13ac00a329a37694a76385903a6f Mon Sep 17 00:00:00 2001
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From: Jim Wilson <[email protected]>
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Date: Thu, 21 Mar 2019 15:08:48 -0700
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Subject: [PATCH 02/11] RISC-V: Fix linker crash in section symbol check.
5+
6+
sym is only set for local symbols. h is only set for global symbols. Gas
7+
won't let me create a global section symbol, but bfd appears to have some
8+
support for that, and I can't rule out that other assemblers might do this.
9+
So we need to support both, and verify sym and h are non-NULL before using.
10+
11+
bfd/
12+
PR 24365
13+
* elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check,
14+
verify sym non-NULL before using. Add identical check using h.
15+
---
16+
bfd/ChangeLog | 6 ++++++
17+
bfd/elfnn-riscv.c | 4 +++-
18+
2 files changed, 9 insertions(+), 1 deletion(-)
19+
20+
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
21+
index 8248394eb2..b47e54de28 100644
22+
--- a/bfd/ChangeLog
23+
+++ b/bfd/ChangeLog
24+
@@ -1,3 +1,9 @@
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+2019-03-21 Jim Wilson <[email protected]>
26+
+
27+
+ PR 24365
28+
+ * elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check,
29+
+ verify sym non-NULL before using. Add identical check using h.
30+
+
31+
2019-02-02 Nick Clifton <[email protected]>
32+
33+
2.32 Release
34+
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
35+
index 69cadaa28c..a08e3243a8 100644
36+
--- a/bfd/elfnn-riscv.c
37+
+++ b/bfd/elfnn-riscv.c
38+
@@ -2059,7 +2059,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
39+
all relocs to update these addends. This is also ambiguous, as
40+
we do allow offsets to be added to the target address, which are
41+
not to be used to find the auipc address. */
42+
- if ((ELF_ST_TYPE (sym->st_info) == STT_SECTION) && rel->r_addend)
43+
+ if (((sym != NULL && (ELF_ST_TYPE (sym->st_info) == STT_SECTION))
44+
+ || (h != NULL && h->type == STT_SECTION))
45+
+ && rel->r_addend)
46+
{
47+
r = bfd_reloc_dangerous;
48+
break;
49+
--
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2.20.1
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‎patches/binutils/2.32/0003-RISC-V-Relax-tail-j-to-c.j-for-RV64.patch‎

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From 8b01621d45bfac0a09fe6ff8a2f4efd734cae334 Mon Sep 17 00:00:00 2001
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From: Jim Wilson <[email protected]>
3+
Date: Sat, 30 Mar 2019 10:12:12 -0700
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Subject: [PATCH 03/11] RISC-V: Relax tail/j to c.j for RV64.
5+
6+
2019-03-30 Andrew Waterman <[email protected]>
7+
bfd/
8+
* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
9+
rd == X_RA case.
10+
---
11+
bfd/ChangeLog | 5 +++++
12+
bfd/elfnn-riscv.c | 7 +++++--
13+
2 files changed, 10 insertions(+), 2 deletions(-)
14+
15+
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
16+
index b47e54de28..8f6cd927e2 100644
17+
--- a/bfd/ChangeLog
18+
+++ b/bfd/ChangeLog
19+
@@ -1,3 +1,8 @@
20+
+2019-03-30 Andrew Waterman <[email protected]>
21+
+
22+
+ * elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
23+
+ rd == X_RA case.
24+
+
25+
2019-03-21 Jim Wilson <[email protected]>
26+
27+
PR 24365
28+
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
29+
index a08e3243a8..5215943ab8 100644
30+
--- a/bfd/elfnn-riscv.c
31+
+++ b/bfd/elfnn-riscv.c
32+
@@ -3416,9 +3416,12 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
33+
auipc = bfd_get_32 (abfd, contents + rel->r_offset);
34+
jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
35+
rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
36+
- rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
37+
+ rvc = rvc && VALID_RVC_J_IMM (foff);
38+
39+
- if (rvc && (rd == 0 || rd == X_RA))
40+
+ /* C.J exists on RV32 and RV64, but C.JAL is RV32-only. */
41+
+ rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
42+
+
43+
+ if (rvc)
44+
{
45+
/* Relax to C.J[AL] rd, addr. */
46+
r_type = R_RISCV_RVC_JUMP;
47+
--
48+
2.20.1
49+

‎patches/binutils/2.32/0004-RISC-V-Don-t-check-ABI-flags-if-no-code-section.patch‎

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From 9a4e806ae727651da00c4e20c7346107221fff7e Mon Sep 17 00:00:00 2001
2+
From: Jim Wilson <[email protected]>
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Date: Tue, 2 Apr 2019 13:30:07 -0700
4+
Subject: [PATCH 04/11] RISC-V: Don't check ABI flags if no code section.
5+
6+
This fixes a glib build failure reported in PR 24389. Using ld -b binary
7+
creates an object file with no elf header flags set which has the wrong ABI
8+
info for riscv64-linux. But the file also has no code sections, so I added
9+
code borrowed from the arm port that only checks the ELF header ABI flags if
10+
there is a code section.
11+
12+
bfd/
13+
PR 24389
14+
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of
15+
ELF header flags to after check for ELF object file. Loop through
16+
sections looking for code sections, if none, then skip ABI checks.
17+
---
18+
bfd/ChangeLog | 7 +++++++
19+
bfd/elfnn-riscv.c | 34 ++++++++++++++++++++++++++++++++--
20+
2 files changed, 39 insertions(+), 2 deletions(-)
21+
22+
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
23+
index 8f6cd927e2..83e9e8ff37 100644
24+
--- a/bfd/ChangeLog
25+
+++ b/bfd/ChangeLog
26+
@@ -1,3 +1,10 @@
27+
+2019-04-02 Jim Wilson <[email protected]>
28+
+
29+
+ PR 24389
30+
+ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of
31+
+ ELF header flags to after check for ELF object file. Loop through
32+
+ sections looking for code sections, if none, then skip ABI checks.
33+
+
34+
2019-03-30 Andrew Waterman <[email protected]>
35+
36+
* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
37+
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
38+
index 5215943ab8..b7d82239fc 100644
39+
--- a/bfd/elfnn-riscv.c
40+
+++ b/bfd/elfnn-riscv.c
41+
@@ -3086,8 +3086,7 @@ static bfd_boolean
42+
_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
43+
{
44+
bfd *obfd = info->output_bfd;
45+
- flagword new_flags = elf_elfheader (ibfd)->e_flags;
46+
- flagword old_flags = elf_elfheader (obfd)->e_flags;
47+
+ flagword new_flags, old_flags;
48+
49+
if (!is_riscv_elf (ibfd) || !is_riscv_elf (obfd))
50+
return TRUE;
51+
@@ -3107,6 +3106,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
52+
if (!riscv_merge_attributes (ibfd, info))
53+
return FALSE;
54+
55+
+ new_flags = elf_elfheader (ibfd)->e_flags;
56+
+ old_flags = elf_elfheader (obfd)->e_flags;
57+
+
58+
if (! elf_flags_init (obfd))
59+
{
60+
elf_flags_init (obfd) = TRUE;
61+
@@ -3114,6 +3116,34 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
62+
return TRUE;
63+
}
64+
65+
+ /* Check to see if the input BFD actually contains any sections. If not,
66+
+ its flags may not have been initialized either, but it cannot actually
67+
+ cause any incompatibility. Do not short-circuit dynamic objects; their
68+
+ section list may be emptied by elf_link_add_object_symbols.
69+
+
70+
+ Also check to see if there are no code sections in the input. In this
71+
+ case, there is no need to check for code specific flags. */
72+
+ if (!(ibfd->flags & DYNAMIC))
73+
+ {
74+
+ bfd_boolean null_input_bfd = TRUE;
75+
+ bfd_boolean only_data_sections = TRUE;
76+
+ asection *sec;
77+
+
78+
+ for (sec = ibfd->sections; sec != NULL; sec = sec->next)
79+
+ {
80+
+ if ((bfd_get_section_flags (ibfd, sec)
81+
+ & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
82+
+ == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
83+
+ only_data_sections = FALSE;
84+
+
85+
+ null_input_bfd = FALSE;
86+
+ break;
87+
+ }
88+
+
89+
+ if (null_input_bfd || only_data_sections)
90+
+ return TRUE;
91+
+ }
92+
+
93+
/* Disallow linking different float ABIs. */
94+
if ((old_flags ^ new_flags) & EF_RISCV_FLOAT_ABI)
95+
{
96+
--
97+
2.20.1
98+

‎patches/binutils/2.32/0005-RISC-V-Enable-32-bit-linux-gdb-core-file-support.patch‎

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From 822d3328bee88b9d2e2970b810af74192b722283 Mon Sep 17 00:00:00 2001
2+
From: Jim Wilson <[email protected]>
3+
Date: Mon, 22 Apr 2019 14:17:55 -0700
4+
Subject: [PATCH 05/11] RISC-V: Enable 32-bit linux gdb core file support.
5+
6+
bfd/
7+
* elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
8+
---
9+
bfd/ChangeLog | 4 ++++
10+
bfd/elfnn-riscv.c | 2 +-
11+
2 files changed, 5 insertions(+), 1 deletion(-)
12+
13+
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
14+
index 83e9e8ff37..0e00f14828 100644
15+
--- a/bfd/ChangeLog
16+
+++ b/bfd/ChangeLog
17+
@@ -1,3 +1,7 @@
18+
+2019-04-22 Jim Wilson <[email protected]>
19+
+
20+
+ * elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
21+
+
22+
2019-04-02 Jim Wilson <[email protected]>
23+
24+
PR 24389
25+
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
26+
index b7d82239fc..7f63a9b034 100644
27+
--- a/bfd/elfnn-riscv.c
28+
+++ b/bfd/elfnn-riscv.c
29+
@@ -4008,7 +4008,7 @@ fail:
30+
}
31+
32+
#if ARCH_SIZE == 32
33+
-# define PRSTATUS_SIZE 0 /* FIXME */
34+
+# define PRSTATUS_SIZE 204
35+
# define PRSTATUS_OFFSET_PR_CURSIG 12
36+
# define PRSTATUS_OFFSET_PR_PID 24
37+
# define PRSTATUS_OFFSET_PR_REG 72
38+
--
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2.20.1
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