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Mathieu Choplainkartben
Mathieu Choplain
authored and
kartben
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dts: arm: st: stm32l1: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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4 files changed

+24
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‎dts/arm/st/l1/stm32l1.dtsi‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@
104104
compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
105105
reg = <0x40023c00 0x400>;
106106
interrupts = <4 0>;
107-
clocks = <&rcc STM32_CLOCK(AHB1, 15U)>;
107+
clocks = <&rcc STM32_CLOCK(AHB1, 15)>;
108108

109109
#address-cells = <1>;
110110
#size-cells = <1>;
@@ -135,7 +135,7 @@
135135
compatible = "st,stm32-rtc";
136136
reg = <0x40002800 0x400>;
137137
interrupts = <41 0>;
138-
clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
138+
clocks = <&rcc STM32_CLOCK(APB1, 28)>;
139139
prescaler = <32768>;
140140
alarms-count = <2>;
141141
alrm-exti-line = <17>;
@@ -145,7 +145,7 @@
145145
usart2: serial@40004400 {
146146
compatible = "st,stm32-usart", "st,stm32-uart";
147147
reg = <0x40004400 0x400>;
148-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
148+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
149149
resets = <&rctl STM32_RESET(APB1, 17U)>;
150150
interrupts = <38 0>;
151151
status = "disabled";
@@ -154,7 +154,7 @@
154154
usart3: serial@40004800 {
155155
compatible = "st,stm32-usart", "st,stm32-uart";
156156
reg = <0x40004800 0x400>;
157-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
157+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
158158
resets = <&rctl STM32_RESET(APB1, 18U)>;
159159
interrupts = <39 0>;
160160
status = "disabled";
@@ -163,7 +163,7 @@
163163
uart4: serial@40004c00 {
164164
compatible = "st,stm32-uart";
165165
reg = <0x40004c00 0x400>;
166-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
166+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
167167
resets = <&rctl STM32_RESET(APB1, 19U)>;
168168
interrupts = <48 0>;
169169
status = "disabled";
@@ -172,7 +172,7 @@
172172
uart5: serial@40005000 {
173173
compatible = "st,stm32-uart";
174174
reg = <0x40005000 0x400>;
175-
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
175+
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
176176
resets = <&rctl STM32_RESET(APB1, 20U)>;
177177
interrupts = <49 0>;
178178
status = "disabled";
@@ -184,7 +184,7 @@
184184
#address-cells = <1>;
185185
#size-cells = <0>;
186186
reg = <0x40005400 0x400>;
187-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
187+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
188188
interrupts = <31 0>, <32 0>;
189189
interrupt-names = "event", "error";
190190
status = "disabled";
@@ -196,7 +196,7 @@
196196
#address-cells = <1>;
197197
#size-cells = <0>;
198198
reg = <0x40005800 0x400>;
199-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
199+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
200200
interrupts = <33 0>, <34 0>;
201201
interrupt-names = "event", "error";
202202
status = "disabled";
@@ -233,7 +233,7 @@
233233
#address-cells = <1>;
234234
#size-cells = <0>;
235235
reg = <0x40013000 0x400>;
236-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
236+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
237237
interrupts = <35 0>;
238238
status = "disabled";
239239
};
@@ -243,15 +243,15 @@
243243
#address-cells = <1>;
244244
#size-cells = <0>;
245245
reg = <0x40003800 0x400>;
246-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
246+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
247247
interrupts = <36 0>;
248248
status = "disabled";
249249
};
250250

251251
usart1: serial@40013800 {
252252
compatible = "st,stm32-usart", "st,stm32-uart";
253253
reg = <0x40013800 0x400>;
254-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
254+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
255255
resets = <&rctl STM32_RESET(APB2, 14U)>;
256256
interrupts = <37 0>;
257257
status = "disabled";
@@ -260,7 +260,7 @@
260260
adc1: adc@40012400 {
261261
compatible = "st,stm32f4-adc", "st,stm32-adc";
262262
reg = <0x40012400 0x400>;
263-
clocks = <&rcc STM32_CLOCK(APB2, 9U)>,
263+
clocks = <&rcc STM32_CLOCK(APB2, 9)>,
264264
<&rcc STM32_SRC_HSI NO_SEL>;
265265
interrupts = <18 0>;
266266
status = "disabled";
@@ -278,7 +278,7 @@
278278
dac1: dac@40007400 {
279279
compatible = "st,stm32-dac";
280280
reg = <0x40007400 0x400>;
281-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
281+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
282282
status = "disabled";
283283
#io-channel-cells = <1>;
284284
};
@@ -448,47 +448,47 @@
448448
gpio-controller;
449449
#gpio-cells = <2>;
450450
reg = <0x40020000 0x400>;
451-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
451+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
452452
};
453453

454454
gpiob: gpio@40020400 {
455455
compatible = "st,stm32-gpio";
456456
gpio-controller;
457457
#gpio-cells = <2>;
458458
reg = <0x40020400 0x400>;
459-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
459+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
460460
};
461461

462462
gpioc: gpio@40020800 {
463463
compatible = "st,stm32-gpio";
464464
gpio-controller;
465465
#gpio-cells = <2>;
466466
reg = <0x40020800 0x400>;
467-
clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
467+
clocks = <&rcc STM32_CLOCK(AHB1, 2)>;
468468
};
469469

470470
gpiod: gpio@40020c00 {
471471
compatible = "st,stm32-gpio";
472472
gpio-controller;
473473
#gpio-cells = <2>;
474474
reg = <0x40020c00 0x400>;
475-
clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
475+
clocks = <&rcc STM32_CLOCK(AHB1, 3)>;
476476
};
477477

478478
gpioe: gpio@40021000 {
479479
compatible = "st,stm32-gpio";
480480
gpio-controller;
481481
#gpio-cells = <2>;
482482
reg = <0x40021000 0x400>;
483-
clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
483+
clocks = <&rcc STM32_CLOCK(AHB1, 4)>;
484484
};
485485

486486
gpioh: gpio@40021400 {
487487
compatible = "st,stm32-gpio";
488488
gpio-controller;
489489
#gpio-cells = <2>;
490490
reg = <0x40021400 0x400>;
491-
clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
491+
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
492492
};
493493
};
494494

@@ -501,7 +501,7 @@
501501
wwdg: watchdog@40002c00 {
502502
compatible = "st,stm32-window-watchdog";
503503
reg = <0x40002C00 0x400>;
504-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
504+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
505505
interrupts = <0 7>;
506506
status = "disabled";
507507
};
@@ -515,7 +515,7 @@
515515
compatible = "st,stm32-dma-v2bis";
516516
#dma-cells = <2>;
517517
reg = <0x40026000 0x400>;
518-
clocks = <&rcc STM32_CLOCK(AHB1, 24U)>;
518+
clocks = <&rcc STM32_CLOCK(AHB1, 24)>;
519519
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
520520
status = "disabled";
521521
};

‎dts/arm/st/l1/stm32l151Xc.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#address-cells = <1>;
4343
#size-cells = <0>;
4444
reg = <0x40003c00 0x400>;
45-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
45+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
4646
interrupts = <47 0>;
4747
status = "disabled";
4848
};

‎dts/arm/st/l1/stm32l152Xc.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#address-cells = <1>;
4343
#size-cells = <0>;
4444
reg = <0x40003c00 0x400>;
45-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
45+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
4646
interrupts = <47 0>;
4747
status = "disabled";
4848
};

‎dts/arm/st/l1/stm32l152Xe.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#address-cells = <1>;
4343
#size-cells = <0>;
4444
reg = <0x40003c00 0x400>;
45-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
45+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
4646
interrupts = <47 0>;
4747
status = "disabled";
4848
};

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