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Mathieu Choplainkartben
Mathieu Choplain
authored and
kartben
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dts: arm: st: stm32l0: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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+30
-30
lines changed

6 files changed

+30
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‎dts/arm/st/l0/stm32l0.dtsi‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@
9696
compatible = "st,stm32-rtc";
9797
reg = <0x40002800 0x400>;
9898
interrupts = <2 0>;
99-
clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
99+
clocks = <&rcc STM32_CLOCK(APB1, 28)>;
100100
prescaler = <32768>;
101101
alarms-count = <2>;
102102
alrm-exti-line = <17>;
@@ -162,39 +162,39 @@
162162
gpio-controller;
163163
#gpio-cells = <2>;
164164
reg = <0x50000000 0x400>;
165-
clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
165+
clocks = <&rcc STM32_CLOCK(IOP, 0)>;
166166
};
167167

168168
gpiob: gpio@50000400 {
169169
compatible = "st,stm32-gpio";
170170
gpio-controller;
171171
#gpio-cells = <2>;
172172
reg = <0x50000400 0x400>;
173-
clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
173+
clocks = <&rcc STM32_CLOCK(IOP, 1)>;
174174
};
175175

176176
gpioc: gpio@50000800 {
177177
compatible = "st,stm32-gpio";
178178
gpio-controller;
179179
#gpio-cells = <2>;
180180
reg = <0x50000800 0x400>;
181-
clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
181+
clocks = <&rcc STM32_CLOCK(IOP, 2)>;
182182
};
183183

184184
gpiod: gpio@50000c00 {
185185
compatible = "st,stm32-gpio";
186186
gpio-controller;
187187
#gpio-cells = <2>;
188188
reg = <0x50000c00 0x400>;
189-
clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
189+
clocks = <&rcc STM32_CLOCK(IOP, 3)>;
190190
};
191191

192192
gpioh: gpio@50001c00 {
193193
compatible = "st,stm32-gpio";
194194
gpio-controller;
195195
#gpio-cells = <2>;
196196
reg = <0x50001c00 0x400>;
197-
clocks = <&rcc STM32_CLOCK(IOP, 7U)>;
197+
clocks = <&rcc STM32_CLOCK(IOP, 7)>;
198198
};
199199
};
200200

@@ -207,15 +207,15 @@
207207
wwdg: watchdog@40002c00 {
208208
compatible = "st,stm32-window-watchdog";
209209
reg = <0x40002C00 0x400>;
210-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
210+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
211211
interrupts = <0 2>;
212212
status = "disabled";
213213
};
214214

215215
usart2: serial@40004400 {
216216
compatible = "st,stm32-usart", "st,stm32-uart";
217217
reg = <0x40004400 0x400>;
218-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
218+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
219219
resets = <&rctl STM32_RESET(APB1, 17U)>;
220220
interrupts = <28 0>;
221221
status = "disabled";
@@ -224,7 +224,7 @@
224224
lpuart1: serial@40004800 {
225225
compatible = "st,stm32-lpuart", "st,stm32-uart";
226226
reg = <0x40004800 0x400>;
227-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
227+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
228228
resets = <&rctl STM32_RESET(APB1, 18U)>;
229229
interrupts = <29 0>;
230230
status = "disabled";
@@ -236,7 +236,7 @@
236236
#address-cells = <1>;
237237
#size-cells = <0>;
238238
reg = <0x40005400 0x400>;
239-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
239+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
240240
interrupts = <23 0>;
241241
interrupt-names = "combined";
242242
status = "disabled";
@@ -247,7 +247,7 @@
247247
#address-cells = <1>;
248248
#size-cells = <0>;
249249
reg = <0x40013000 0x400>;
250-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
250+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
251251
interrupts = <25 3>;
252252
status = "disabled";
253253
};
@@ -300,7 +300,7 @@
300300

301301
lptim1: timers@40007c00 {
302302
compatible = "st,stm32-lptim";
303-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
303+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
304304
#address-cells = <1>;
305305
#size-cells = <0>;
306306
reg = <0x40007c00 0x400>;
@@ -312,7 +312,7 @@
312312
adc1: adc@40012400 {
313313
compatible = "st,stm32-adc";
314314
reg = <0x40012400 0x400>;
315-
clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
315+
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
316316
interrupts = <12 0>;
317317
status = "disabled";
318318
#io-channel-cells = <1>;
@@ -331,7 +331,7 @@
331331
#dma-cells = <3>;
332332
reg = <0x40020000 0x400>;
333333
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
334-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
334+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
335335
status = "disabled";
336336
};
337337

‎dts/arm/st/l0/stm32l031.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
timers22: timers@40011400 {
1414
compatible = "st,stm32-timers";
1515
reg = <0x40011400 0x400>;
16-
clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
16+
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
1717
resets = <&rctl STM32_RESET(APB2, 5U)>;
1818
interrupts = <22 0>;
1919
interrupt-names = "global";

‎dts/arm/st/l0/stm32l051.dtsi‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
#address-cells = <1>;
1717
#size-cells = <0>;
1818
reg = <0x40005800 0x400>;
19-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
19+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
2020
interrupts = <24 0>;
2121
interrupt-names = "combined";
2222
status = "disabled";
@@ -27,15 +27,15 @@
2727
#address-cells = <1>;
2828
#size-cells = <0>;
2929
reg = <0x40003800 0x400>;
30-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
30+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
3131
interrupts = <26 3>;
3232
status = "disabled";
3333
};
3434

3535
usart1: serial@40013800 {
3636
compatible = "st,stm32-usart", "st,stm32-uart";
3737
reg = <0x40013800 0x400>;
38-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
38+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
3939
resets = <&rctl STM32_RESET(APB2, 14U)>;
4040
interrupts = <27 0>;
4141
status = "disabled";

‎dts/arm/st/l0/stm32l053.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,15 +29,15 @@
2929
ram-size = <1024>;
3030
maximum-speed = "full-speed";
3131
phys = <&otgfs_phy>;
32-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
32+
clocks = <&rcc STM32_CLOCK(APB1, 23)>,
3333
<&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
3434
status = "disabled";
3535
};
3636

3737
dac1: dac@40007400 {
3838
compatible = "st,stm32-dac";
3939
reg = <0x40007400 0x400>;
40-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
40+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
4141
status = "disabled";
4242
#io-channel-cells = <1>;
4343
};

‎dts/arm/st/l0/stm32l071.dtsi‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
gpio-controller;
1717
#gpio-cells = <2>;
1818
reg = <0x50001000 0x400>;
19-
clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
19+
clocks = <&rcc STM32_CLOCK(IOP, 4)>;
2020
};
2121
};
2222

@@ -26,7 +26,7 @@
2626
#address-cells = <1>;
2727
#size-cells = <0>;
2828
reg = <0x40005800 0x400>;
29-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
29+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
3030
interrupts = <24 0>;
3131
interrupt-names = "combined";
3232
status = "disabled";
@@ -38,7 +38,7 @@
3838
#address-cells = <1>;
3939
#size-cells = <0>;
4040
reg = <0x40007800 0x400>;
41-
clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
41+
clocks = <&rcc STM32_CLOCK(APB1, 30)>;
4242
interrupts = <21 0>;
4343
interrupt-names = "combined";
4444
status = "disabled";
@@ -49,7 +49,7 @@
4949
#address-cells = <1>;
5050
#size-cells = <0>;
5151
reg = <0x40003800 0x400>;
52-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
52+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
5353
interrupts = <26 3>;
5454
status = "disabled";
5555
};
@@ -137,7 +137,7 @@
137137
usart1: serial@40013800 {
138138
compatible = "st,stm32-usart", "st,stm32-uart";
139139
reg = <0x40013800 0x400>;
140-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
140+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
141141
resets = <&rctl STM32_RESET(APB2, 14U)>;
142142
interrupts = <27 0>;
143143
status = "disabled";
@@ -146,7 +146,7 @@
146146
usart4: serial@40004c00 {
147147
compatible = "st,stm32-usart", "st,stm32-uart";
148148
reg = <0x40004c00 0x400>;
149-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
149+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
150150
resets = <&rctl STM32_RESET(APB1, 19U)>;
151151
interrupts = <14 0>;
152152
status = "disabled";
@@ -155,7 +155,7 @@
155155
usart5: serial@40005000 {
156156
compatible = "st,stm32-usart", "st,stm32-uart";
157157
reg = <0x40005000 0x400>;
158-
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
158+
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
159159
resets = <&rctl STM32_RESET(APB1, 20U)>;
160160
interrupts = <14 0>;
161161
status = "disabled";

‎dts/arm/st/l0/stm32l072.dtsi‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
ram-size = <1024>;
3333
maximum-speed = "full-speed";
3434
phys = <&otgfs_phy>;
35-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
35+
clocks = <&rcc STM32_CLOCK(APB1, 23)>,
3636
<&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
3737
status = "disabled";
3838
};
@@ -41,7 +41,7 @@
4141
compatible = "st,stm32-rng";
4242
reg = <0x40025000 0x400>;
4343
interrupts = <29 0>;
44-
clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
44+
clocks = <&rcc STM32_CLOCK(AHB1, 20)>;
4545
status = "disabled";
4646
};
4747
};
@@ -54,7 +54,7 @@
5454
dac1: dac@40007400 {
5555
compatible = "st,stm32-dac";
5656
reg = <0x40007400 0x400>;
57-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
57+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
5858
status = "disabled";
5959
#io-channel-cells = <1>;
6060
};

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