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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32u0: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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‎dts/arm/st/u0/stm32u0.dtsi‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -168,54 +168,54 @@
168168
gpio-controller;
169169
#gpio-cells = <2>;
170170
reg = <0x50000000 0x400>;
171-
clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
171+
clocks = <&rcc STM32_CLOCK(IOP, 0)>;
172172
};
173173

174174
gpiob: gpio@50000400 {
175175
compatible = "st,stm32-gpio";
176176
gpio-controller;
177177
#gpio-cells = <2>;
178178
reg = <0x50000400 0x400>;
179-
clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
179+
clocks = <&rcc STM32_CLOCK(IOP, 1)>;
180180
};
181181

182182
gpioc: gpio@50000800 {
183183
compatible = "st,stm32-gpio";
184184
gpio-controller;
185185
#gpio-cells = <2>;
186186
reg = <0x50000800 0x400>;
187-
clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
187+
clocks = <&rcc STM32_CLOCK(IOP, 2)>;
188188
};
189189

190190
gpiod: gpio@50000C00 {
191191
compatible = "st,stm32-gpio";
192192
gpio-controller;
193193
#gpio-cells = <2>;
194194
reg = <0x50000C00 0x400>;
195-
clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
195+
clocks = <&rcc STM32_CLOCK(IOP, 3)>;
196196
};
197197

198198
gpioe: gpio@50001000 {
199199
compatible = "st,stm32-gpio";
200200
gpio-controller;
201201
#gpio-cells = <2>;
202202
reg = <0x50001000 0x400>;
203-
clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
203+
clocks = <&rcc STM32_CLOCK(IOP, 4)>;
204204
};
205205

206206
gpiof: gpio@50001400 {
207207
compatible = "st,stm32-gpio";
208208
gpio-controller;
209209
#gpio-cells = <2>;
210210
reg = <0x50001400 0x400>;
211-
clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
211+
clocks = <&rcc STM32_CLOCK(IOP, 5)>;
212212
};
213213
};
214214

215215
usart1: serial@40013800 {
216216
compatible = "st,stm32-usart", "st,stm32-uart";
217217
reg = <0x40013800 0x400>;
218-
clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
218+
clocks = <&rcc STM32_CLOCK(APB1_2, 14)>;
219219
resets = <&rctl STM32_RESET(APB1H, 14U)>;
220220
interrupts = <27 0>;
221221
status = "disabled";
@@ -224,7 +224,7 @@
224224
usart2: serial@40004400 {
225225
compatible = "st,stm32-usart", "st,stm32-uart";
226226
reg = <0x40004400 0x400>;
227-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
227+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
228228
resets = <&rctl STM32_RESET(APB1L, 17U)>;
229229
interrupts = <28 0>;
230230
status = "disabled";
@@ -233,7 +233,7 @@
233233
usart3: serial@40004800 {
234234
compatible = "st,stm32-usart", "st,stm32-uart";
235235
reg = <0x40004800 0x400>;
236-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
236+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
237237
resets = <&rctl STM32_RESET(APB1L, 18U)>;
238238
interrupts = <29 0>;
239239
status = "disabled";
@@ -242,7 +242,7 @@
242242
usart4: serial@40004c00 {
243243
compatible = "st,stm32-usart", "st,stm32-uart";
244244
reg = <0x40004c00 0x400>;
245-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
245+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
246246
resets = <&rctl STM32_RESET(APB1L, 19U)>;
247247
interrupts = <30 0>;
248248
status = "disabled";
@@ -251,7 +251,7 @@
251251
lpuart1: serial@40008000 {
252252
compatible = "st,stm32-lpuart", "st,stm32-uart";
253253
reg = <0x40008000 0x400>;
254-
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
254+
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
255255
resets = <&rctl STM32_RESET(APB1L, 20U)>;
256256
interrupts = <29 0>;
257257
status = "disabled";
@@ -260,7 +260,7 @@
260260
lpuart2: serial@40008400 {
261261
compatible = "st,stm32-lpuart", "st,stm32-uart";
262262
reg = <0x40008400 0x400>;
263-
clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
263+
clocks = <&rcc STM32_CLOCK(APB1, 7)>;
264264
resets = <&rctl STM32_RESET(APB1L, 7U)>;
265265
interrupts = <28 0>;
266266
status = "disabled";
@@ -275,15 +275,15 @@
275275
wwdg: watchdog@40002c00 {
276276
compatible = "st,stm32-window-watchdog";
277277
reg = <0x40002c00 0x400>;
278-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
278+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
279279
interrupts = <0 7>;
280280
status = "disabled";
281281
};
282282

283283
adc1: adc@40012400 {
284284
compatible = "st,stm32-adc";
285285
reg = <0x40012400 0x400>;
286-
clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
286+
clocks = <&rcc STM32_CLOCK(APB1_2, 20)>;
287287
interrupts = <12 0>;
288288
status = "disabled";
289289
#io-channel-cells = <1>;
@@ -300,7 +300,7 @@
300300
dac1: dac@40007400 {
301301
compatible = "st,stm32-dac";
302302
reg = <0x40007400 0x400>;
303-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
303+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
304304
status = "disabled";
305305
#io-channel-cells = <1>;
306306
};
@@ -311,7 +311,7 @@
311311
#address-cells = <1>;
312312
#size-cells = <0>;
313313
reg = <0x40005400 0x400>;
314-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
314+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
315315
interrupts = <23 0>;
316316
interrupt-names = "combined";
317317
status = "disabled";
@@ -323,7 +323,7 @@
323323
#address-cells = <1>;
324324
#size-cells = <0>;
325325
reg = <0x40005800 0x400>;
326-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
326+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
327327
interrupts = <24 0>;
328328
interrupt-names = "combined";
329329
status = "disabled";
@@ -335,7 +335,7 @@
335335
#address-cells = <1>;
336336
#size-cells = <0>;
337337
reg = <0x40008800 0x400>;
338-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
338+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
339339
interrupts = <24 0>;
340340
interrupt-names = "combined";
341341
status = "disabled";
@@ -346,7 +346,7 @@
346346
#dma-cells = <3>;
347347
reg = <0x40020000 0x400>;
348348
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
349-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
349+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
350350
dma-requests = <7>;
351351
dma-offset = <0>;
352352
status = "disabled";
@@ -368,7 +368,7 @@
368368
#address-cells = <1>;
369369
#size-cells = <0>;
370370
reg = <0x40013000 0x400>;
371-
clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
371+
clocks = <&rcc STM32_CLOCK(APB1_2, 12)>;
372372
interrupts = <25 0>;
373373
status = "disabled";
374374
};
@@ -378,7 +378,7 @@
378378
#address-cells = <1>;
379379
#size-cells = <0>;
380380
reg = <0x40003800 0x400>;
381-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
381+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
382382
interrupts = <26 0>;
383383
status = "disabled";
384384
};
@@ -388,23 +388,23 @@
388388
#address-cells = <1>;
389389
#size-cells = <0>;
390390
reg = <0x40003c00 0x400>;
391-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
391+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
392392
interrupts = <26 0>;
393393
status = "disabled";
394394
};
395395

396396
rng: rng@40025000 {
397397
compatible = "st,stm32-rng";
398398
reg = <0x40025000 0x400>;
399-
clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
399+
clocks = <&rcc STM32_CLOCK(AHB1, 18)>;
400400
interrupts = <31 0>;
401401
status = "disabled";
402402
};
403403

404404
aes: aes@40026000 {
405405
compatible = "st,stm32-aes";
406406
reg = <0x40026000 0x400>;
407-
clocks = <&rcc STM32_CLOCK(AHB1, 16U)>;
407+
clocks = <&rcc STM32_CLOCK(AHB1, 16)>;
408408
resets = <&rctl STM32_RESET(AHB1, 16U)>;
409409
interrupts = <31 0>;
410410
interrupt-names = "aes";
@@ -415,7 +415,7 @@
415415
compatible = "st,stm32-rtc";
416416
reg = <0x40002800 0x400>;
417417
interrupts = <2 0>;
418-
clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
418+
clocks = <&rcc STM32_CLOCK(APB1, 10)>;
419419
prescaler = <32768>;
420420
alarms-count = <2>;
421421
alrm-exti-line = <28>;
@@ -563,7 +563,7 @@
563563

564564
lptim1: timers@40007c00 {
565565
compatible = "st,stm32-lptim";
566-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
566+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
567567
#address-cells = <1>;
568568
#size-cells = <0>;
569569
reg = <0x40007c00 0x400>;
@@ -575,7 +575,7 @@
575575

576576
lptim2: timers@40009400 {
577577
compatible = "st,stm32-lptim";
578-
clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
578+
clocks = <&rcc STM32_CLOCK(APB1, 30)>;
579579
#address-cells = <1>;
580580
#size-cells = <0>;
581581
reg = <0x40009400 0x400>;
@@ -587,7 +587,7 @@
587587
tsc: tsc@40024000 {
588588
compatible = "st,stm32-tsc";
589589
reg = <0x40024000 0x400>;
590-
clocks = <&rcc STM32_CLOCK(AHB1, 24U)>;
590+
clocks = <&rcc STM32_CLOCK(AHB1, 24)>;
591591
resets = <&rctl STM32_RESET(AHB1, 24U)>;
592592
interrupts = <21 0>;
593593
interrupt-names = "global";

‎dts/arm/st/u0/stm32u073.dtsi‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,15 +16,15 @@
1616
#address-cells = <1>;
1717
#size-cells = <0>;
1818
reg = <0x4000a000 0x400>;
19-
clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
19+
clocks = <&rcc STM32_CLOCK(APB1, 25)>;
2020
interrupts = <24 0>;
2121
interrupt-names = "combined";
2222
status = "disabled";
2323
};
2424

2525
lptim3: timers@40009000 {
2626
compatible = "st,stm32-lptim";
27-
clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
27+
clocks = <&rcc STM32_CLOCK(APB1, 26)>;
2828
#address-cells = <1>;
2929
#size-cells = <0>;
3030
reg = <0x40009000 0x400>;
@@ -38,7 +38,7 @@
3838
#dma-cells = <3>;
3939
reg = <0x40020400 0x400>;
4040
interrupts = <11 0 11 0 11 0 11 0 11 0>;
41-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
41+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
4242
dma-requests = <5>;
4343
dma-offset = <7>;
4444
status = "disabled";
@@ -57,7 +57,7 @@
5757
ram-size = <1024>;
5858
maximum-speed = "full-speed";
5959
phys = <&usb_fs_phy>;
60-
clocks = <&rcc STM32_CLOCK(APB1, 13U)>;
60+
clocks = <&rcc STM32_CLOCK(APB1, 13)>;
6161
status = "disabled";
6262
};
6363
};

‎dts/arm/st/u0/stm32u083.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
lpuart3: serial@40008c00 {
1414
compatible = "st,stm32-lpuart", "st,stm32-uart";
1515
reg = <0x40008c00 0x400>;
16-
clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
16+
clocks = <&rcc STM32_CLOCK(APB1, 12)>;
1717
resets = <&rctl STM32_RESET(APB1L, 12U)>;
1818
interrupts = <30 0>;
1919
status = "disabled";

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