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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32mp1: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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‎dts/arm/st/mp1/stm32mp157.dtsi‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -87,94 +87,94 @@
8787
reg = <0x50002000 0x400>;
8888
gpio-controller;
8989
#gpio-cells = <2>;
90-
clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
90+
clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
9191
};
9292

9393
gpiob: gpio@50003000 {
9494
compatible = "st,stm32-gpio";
9595
reg = <0x50003000 0x400>;
9696
gpio-controller;
9797
#gpio-cells = <2>;
98-
clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
98+
clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
9999
};
100100

101101
gpioc: gpio@50004000 {
102102
compatible = "st,stm32-gpio";
103103
reg = <0x50004000 0x400>;
104104
gpio-controller;
105105
#gpio-cells = <2>;
106-
clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
106+
clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
107107
};
108108

109109
gpiod: gpio@50005000 {
110110
compatible = "st,stm32-gpio";
111111
reg = <0x50005000 0x400>;
112112
gpio-controller;
113113
#gpio-cells = <2>;
114-
clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
114+
clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
115115
};
116116

117117
gpioe: gpio@50006000 {
118118
compatible = "st,stm32-gpio";
119119
reg = <0x50006000 0x400>;
120120
gpio-controller;
121121
#gpio-cells = <2>;
122-
clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
122+
clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
123123
};
124124

125125
gpiof: gpio@50007000 {
126126
compatible = "st,stm32-gpio";
127127
reg = <0x50007000 0x400>;
128128
gpio-controller;
129129
#gpio-cells = <2>;
130-
clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
130+
clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
131131
};
132132

133133
gpiog: gpio@50008000 {
134134
compatible = "st,stm32-gpio";
135135
reg = <0x50008000 0x400>;
136136
gpio-controller;
137137
#gpio-cells = <2>;
138-
clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
138+
clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
139139
};
140140

141141
gpioh: gpio@50009000 {
142142
compatible = "st,stm32-gpio";
143143
reg = <0x50009000 0x400>;
144144
gpio-controller;
145145
#gpio-cells = <2>;
146-
clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
146+
clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
147147
};
148148

149149
gpioi: gpio@5000a000 {
150150
compatible = "st,stm32-gpio";
151151
reg = <0x5000a000 0x400>;
152152
gpio-controller;
153153
#gpio-cells = <2>;
154-
clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
154+
clocks = <&rcc STM32_CLOCK(AHB4, 8)>;
155155
};
156156

157157
gpioj: gpio@5000b000 {
158158
compatible = "st,stm32-gpio";
159159
reg = <0x5000b000 0x400>;
160160
gpio-controller;
161161
#gpio-cells = <2>;
162-
clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
162+
clocks = <&rcc STM32_CLOCK(AHB4, 9)>;
163163
};
164164

165165
gpiok: gpio@5000c000 {
166166
compatible = "st,stm32-gpio";
167167
reg = <0x5000c000 0x400>;
168168
gpio-controller;
169169
#gpio-cells = <2>;
170-
clocks = <&rcc STM32_CLOCK(AHB4, 10U)>;
170+
clocks = <&rcc STM32_CLOCK(AHB4, 10)>;
171171
};
172172
};
173173

174174
wwdg: wwdg1: watchdog@4000a000 {
175175
compatible = "st,stm32-window-watchdog";
176176
reg = <0x4000a000 0x400>;
177-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
177+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
178178
interrupts = <0 7>;
179179
status = "disabled";
180180
};
@@ -183,7 +183,7 @@
183183
compatible = "st,stm32-dma-v1";
184184
#dma-cells = <4>;
185185
reg = <0x48000000 0x400>;
186-
clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
186+
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
187187
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
188188
dma-offset = <0>;
189189
dma-requests = <8>;
@@ -194,7 +194,7 @@
194194
compatible = "st,stm32-dma-v1";
195195
#dma-cells = <4>;
196196
reg = <0x48001000 0x400>;
197-
clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
197+
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
198198
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
199199
dma-offset = <8>;
200200
dma-requests = <8>;
@@ -205,7 +205,7 @@
205205
compatible = "st,stm32-dmamux";
206206
#dma-cells = <3>;
207207
reg = <0x48002000 0x400>;
208-
clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
208+
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
209209
interrupts = <102 0>;
210210
dma-channels = <16>;
211211
dma-generators = <8>;
@@ -218,7 +218,7 @@
218218
reg = <0x44004000 0x400>;
219219
#address-cells = <1>;
220220
#size-cells = <0>;
221-
clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
221+
clocks = <&rcc STM32_CLOCK(APB2, 8)>;
222222
interrupts = <35 5>;
223223
status = "disabled";
224224
};
@@ -228,7 +228,7 @@
228228
reg = <0x4000b000 0x400>;
229229
#address-cells = <1>;
230230
#size-cells = <0>;
231-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
231+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
232232
interrupts = <36 5>;
233233
status = "disabled";
234234
};
@@ -238,7 +238,7 @@
238238
reg = <0x4000c000 0x400>;
239239
#address-cells = <1>;
240240
#size-cells = <0>;
241-
clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
241+
clocks = <&rcc STM32_CLOCK(APB1, 12)>;
242242
interrupts = <51 5>;
243243
status = "disabled";
244244
};
@@ -248,7 +248,7 @@
248248
reg = <0x44005000 0x400>;
249249
#address-cells = <1>;
250250
#size-cells = <0>;
251-
clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
251+
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
252252
interrupts = <84 5>;
253253
status = "disabled";
254254
};
@@ -258,15 +258,15 @@
258258
reg = <0x44009000 0x400>;
259259
#address-cells = <1>;
260260
#size-cells = <0>;
261-
clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
261+
clocks = <&rcc STM32_CLOCK(APB2, 10)>;
262262
interrupts = <85 5>;
263263
status = "disabled";
264264
};
265265

266266
usart2: serial@4000e000 {
267267
compatible = "st,stm32-usart", "st,stm32-uart";
268268
reg = <0x4000e000 0x400>;
269-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
269+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
270270
resets = <&rctl STM32_RESET(APB1, 14U)>;
271271
interrupts = <38 0>;
272272
status = "disabled";
@@ -275,7 +275,7 @@
275275
usart3: serial@4000f000 {
276276
compatible = "st,stm32-usart", "st,stm32-uart";
277277
reg = <0x4000f000 0x400>;
278-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
278+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
279279
resets = <&rctl STM32_RESET(APB1, 15U)>;
280280
interrupts = <39 0>;
281281
status = "disabled";
@@ -284,7 +284,7 @@
284284
uart4: serial@40010000 {
285285
compatible = "st,stm32-uart";
286286
reg = <0x40010000 0x400>;
287-
clocks = <&rcc STM32_CLOCK(APB1, 16U)>;
287+
clocks = <&rcc STM32_CLOCK(APB1, 16)>;
288288
resets = <&rctl STM32_RESET(APB1, 16U)>;
289289
interrupts = <52 0>;
290290
status = "disabled";
@@ -293,7 +293,7 @@
293293
uart5: serial@40011000 {
294294
compatible = "st,stm32-uart";
295295
reg = <0x40011000 0x400>;
296-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
296+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
297297
resets = <&rctl STM32_RESET(APB1, 17U)>;
298298
interrupts = <53 0>;
299299
status = "disabled";
@@ -302,7 +302,7 @@
302302
usart6: serial@44003000 {
303303
compatible = "st,stm32-usart", "st,stm32-uart";
304304
reg = <0x44003000 0x400>;
305-
clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
305+
clocks = <&rcc STM32_CLOCK(APB2, 13)>;
306306
resets = <&rctl STM32_RESET(APB2, 13U)>;
307307
interrupts = <71 0>;
308308
status = "disabled";
@@ -311,7 +311,7 @@
311311
uart7: serial@40018000 {
312312
compatible = "st,stm32-uart";
313313
reg = <0x40018000 0x400>;
314-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
314+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
315315
resets = <&rctl STM32_RESET(APB1, 18U)>;
316316
interrupts = <82 0>;
317317
status = "disabled";
@@ -320,7 +320,7 @@
320320
uart8: serial@40019000 {
321321
compatible = "st,stm32-uart";
322322
reg = <0x40019000 0x400>;
323-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
323+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
324324
resets = <&rctl STM32_RESET(APB1, 19U)>;
325325
interrupts = <83 0>;
326326
status = "disabled";
@@ -332,7 +332,7 @@
332332
reg = <0x40015000 0x400>;
333333
#address-cells = <1>;
334334
#size-cells = <0>;
335-
clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
335+
clocks = <&rcc STM32_CLOCK(APB1, 24)>;
336336
interrupt-names = "event", "error";
337337
interrupts = <107 0>, <108 0>;
338338
status = "disabled";
@@ -341,7 +341,7 @@
341341
timers3: timers@40001000 {
342342
compatible = "st,stm32-timers";
343343
reg = <0x40001000 0x400>;
344-
clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
344+
clocks = <&rcc STM32_CLOCK(APB1, 1)>;
345345
resets = <&rctl STM32_RESET(APB1, 1U)>;
346346
interrupts = <29 0>;
347347
interrupt-names = "global";
@@ -363,7 +363,7 @@
363363
timers5: timers@40003000 {
364364
compatible = "st,stm32-timers";
365365
reg = <0x40003000 0x400>;
366-
clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
366+
clocks = <&rcc STM32_CLOCK(APB1, 3)>;
367367
resets = <&rctl STM32_RESET(APB1, 3U)>;
368368
interrupts = <50 0>;
369369
interrupt-names = "global";
@@ -385,7 +385,7 @@
385385
mailbox: mailbox@4c001000 {
386386
compatible = "st,stm32-ipcc-mailbox";
387387
reg = <0x4c001000 0x400>;
388-
clocks = <&rcc STM32_CLOCK(AHB3, 12U)>;
388+
clocks = <&rcc STM32_CLOCK(AHB3, 12)>;
389389
interrupts = <103 0>, <104 0>;
390390
interrupt-names = "rxo", "txf";
391391
status = "disabled";
@@ -396,7 +396,7 @@
396396
reg = <0x5a001000 0x200>;
397397
interrupts = <88 0>, <89 0>;
398398
interrupt-names = "ltdc", "ltdc_er";
399-
clocks = <&rcc STM32_CLOCK(APB4, 0U)>;
399+
clocks = <&rcc STM32_CLOCK(APB4, 0)>;
400400
resets = <&rctl STM32_RESET(APB4, 26U)>;
401401
status = "disabled";
402402
};

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