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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32l5: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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‎dts/arm/st/l5/stm32l5.dtsi‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@
125125
compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
126126
reg = <0x40022000 0x400>;
127127
interrupts = <6 0>;
128-
clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
128+
clocks = <&rcc STM32_CLOCK(AHB1, 8)>;
129129

130130
#address-cells = <1>;
131131
#size-cells = <1>;
@@ -188,63 +188,63 @@
188188
gpio-controller;
189189
#gpio-cells = <2>;
190190
reg = <0x42020000 0x400>;
191-
clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
191+
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
192192
};
193193

194194
gpiob: gpio@42020400 {
195195
compatible = "st,stm32-gpio";
196196
gpio-controller;
197197
#gpio-cells = <2>;
198198
reg = <0x42020400 0x400>;
199-
clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
199+
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
200200
};
201201

202202
gpioc: gpio@42020800 {
203203
compatible = "st,stm32-gpio";
204204
gpio-controller;
205205
#gpio-cells = <2>;
206206
reg = <0x42020800 0x400>;
207-
clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
207+
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
208208
};
209209

210210
gpiod: gpio@42020c00 {
211211
compatible = "st,stm32-gpio";
212212
gpio-controller;
213213
#gpio-cells = <2>;
214214
reg = <0x42020c00 0x400>;
215-
clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
215+
clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
216216
};
217217

218218
gpioe: gpio@42021000 {
219219
compatible = "st,stm32-gpio";
220220
gpio-controller;
221221
#gpio-cells = <2>;
222222
reg = <0x42021000 0x400>;
223-
clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
223+
clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
224224
};
225225

226226
gpiof: gpio@42021400 {
227227
compatible = "st,stm32-gpio";
228228
gpio-controller;
229229
#gpio-cells = <2>;
230230
reg = <0x42021400 0x400>;
231-
clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
231+
clocks = <&rcc STM32_CLOCK(AHB2, 5)>;
232232
};
233233

234234
gpiog: gpio@42021800 {
235235
compatible = "st,stm32-gpio";
236236
gpio-controller;
237237
#gpio-cells = <2>;
238238
reg = <0x42021800 0x400>;
239-
clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
239+
clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
240240
};
241241

242242
gpioh: gpio@42021c00 {
243243
compatible = "st,stm32-gpio";
244244
gpio-controller;
245245
#gpio-cells = <2>;
246246
reg = <0x42021c00 0x400>;
247-
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
247+
clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
248248
};
249249
};
250250

@@ -257,15 +257,15 @@
257257
wwdg: watchdog@40002c00 {
258258
compatible = "st,stm32-window-watchdog";
259259
reg = <0x40002C00 0x400>;
260-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
260+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
261261
interrupts = <0 6>;
262262
status = "disabled";
263263
};
264264

265265
usart1: serial@40013800 {
266266
compatible = "st,stm32-usart", "st,stm32-uart";
267267
reg = <0x40013800 0x400>;
268-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
268+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
269269
resets = <&rctl STM32_RESET(APB2, 14U)>;
270270
interrupts = <61 0>;
271271
status = "disabled";
@@ -274,7 +274,7 @@
274274
usart2: serial@40004400 {
275275
compatible = "st,stm32-usart", "st,stm32-uart";
276276
reg = <0x40004400 0x400>;
277-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
277+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
278278
resets = <&rctl STM32_RESET(APB1L, 17U)>;
279279
interrupts = <62 0>;
280280
status = "disabled";
@@ -283,7 +283,7 @@
283283
usart3: serial@40004800 {
284284
compatible = "st,stm32-usart", "st,stm32-uart";
285285
reg = <0x40004800 0x400>;
286-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
286+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
287287
resets = <&rctl STM32_RESET(APB1L, 18U)>;
288288
interrupts = <63 0>;
289289
status = "disabled";
@@ -292,7 +292,7 @@
292292
uart4: serial@40004c00 {
293293
compatible = "st,stm32-uart";
294294
reg = <0x40004c00 0x400>;
295-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
295+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
296296
resets = <&rctl STM32_RESET(APB1L, 19U)>;
297297
interrupts = <64 0>;
298298
status = "disabled";
@@ -301,7 +301,7 @@
301301
uart5: serial@40005000 {
302302
compatible = "st,stm32-uart";
303303
reg = <0x40005000 0x400>;
304-
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
304+
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
305305
resets = <&rctl STM32_RESET(APB1L, 20U)>;
306306
interrupts = <65 0>;
307307
status = "disabled";
@@ -310,15 +310,15 @@
310310
lpuart1: serial@40008000 {
311311
compatible = "st,stm32-lpuart", "st,stm32-uart";
312312
reg = <0x40008000 0x400>;
313-
clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
313+
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
314314
resets = <&rctl STM32_RESET(APB1H, 0U)>;
315315
interrupts = <66 0>;
316316
status = "disabled";
317317
};
318318

319319
lptim1: timers@40007c00 {
320320
compatible = "st,stm32-lptim";
321-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
321+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
322322
#address-cells = <1>;
323323
#size-cells = <0>;
324324
reg = <0x40007c00 0x400>;
@@ -332,7 +332,7 @@
332332
#dma-cells = <3>;
333333
reg = <0x40020000 0x400>;
334334
interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>;
335-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
335+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
336336
dma-requests = <8>;
337337
dma-offset = <0>;
338338
status = "disabled";
@@ -343,7 +343,7 @@
343343
#dma-cells = <3>;
344344
reg = <0x40020400 0x400>;
345345
interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
346-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
346+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
347347
dma-requests = <8>;
348348
dma-offset = <8>;
349349
status = "disabled";
@@ -354,7 +354,7 @@
354354
#dma-cells = <3>;
355355
reg = <0x40020800 0x400>;
356356
interrupts = <27 0>;
357-
clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
357+
clocks = <&rcc STM32_CLOCK(AHB1, 2)>;
358358
dma-channels = <16>;
359359
dma-generators = <4>;
360360
dma-requests= <90>;
@@ -367,7 +367,7 @@
367367
#address-cells = <1>;
368368
#size-cells = <0>;
369369
reg = <0x40005400 0x400>;
370-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
370+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
371371
interrupts = <55 0>, <56 0>;
372372
interrupt-names = "event", "error";
373373
status = "disabled";
@@ -379,7 +379,7 @@
379379
#size-cells = <0>;
380380
clock-frequency = <I2C_BITRATE_STANDARD>;
381381
reg = <0x40005800 0x400>;
382-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
382+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
383383
interrupts = <57 0>, <58 0>;
384384
interrupt-names = "event", "error";
385385
status = "disabled";
@@ -391,14 +391,14 @@
391391
#size-cells = <0>;
392392
reg = <0x40013000 0x400>;
393393
interrupts = <59 5>;
394-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
394+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
395395
status = "disabled";
396396
};
397397

398398
sdmmc1: sdmmc@420c8000 {
399399
compatible = "st,stm32-sdmmc";
400400
reg = <0x420c8000 0x400>;
401-
clocks = <&rcc STM32_CLOCK(AHB2, 22U)>,
401+
clocks = <&rcc STM32_CLOCK(AHB2, 22)>,
402402
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
403403
resets = <&rctl STM32_RESET(AHB2, 22U)>;
404404
interrupts = <78 0>;
@@ -408,7 +408,7 @@
408408
dac1: dac@40007400 {
409409
compatible = "st,stm32-dac";
410410
reg = <0x40007400 0x400>;
411-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
411+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
412412
status = "disabled";
413413
#io-channel-cells = <1>;
414414
};
@@ -419,7 +419,7 @@
419419
#size-cells = <0>;
420420
reg = <0x40003800 0x400>;
421421
interrupts = <60 5>;
422-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
422+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
423423
status = "disabled";
424424
};
425425

@@ -429,7 +429,7 @@
429429
#size-cells = <0>;
430430
reg = <0x40003c00 0x400>;
431431
interrupts = <99 5>;
432-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
432+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
433433
status = "disabled";
434434
};
435435

@@ -438,7 +438,7 @@
438438
reg = <0x44021000 0x400>, <0x90000000 DT_SIZE_M(256)>;
439439
interrupts = <76 0>;
440440
clock-names = "ospix", "ospi-ker";
441-
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
441+
clocks = <&rcc STM32_CLOCK(AHB3, 8)>,
442442
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>;
443443
#address-cells = <1>;
444444
#size-cells = <0>;
@@ -449,7 +449,7 @@
449449
compatible = "st,stm32-rng";
450450
reg = <0x420c0800 0x400>;
451451
interrupts = <94 0>;
452-
clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
452+
clocks = <&rcc STM32_CLOCK(AHB2, 18)>;
453453
nist-config = <0xf00d00>;
454454
health-test-magic = <0x17590abc>;
455455
health-test-config = <0xa2b3>;
@@ -460,7 +460,7 @@
460460
compatible = "st,stm32-rtc";
461461
reg = <0x40002800 0x400>;
462462
interrupts = <2 0>;
463-
clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
463+
clocks = <&rcc STM32_CLOCK(APB1, 10)>;
464464
prescaler = <32768>;
465465
alarms-count = <2>;
466466
alrm-exti-line = <17>;
@@ -667,7 +667,7 @@
667667
adc1: adc@42028000 {
668668
compatible = "st,stm32-adc";
669669
reg = <0x42028000 0x100>;
670-
clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
670+
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
671671
interrupts = <37 0>;
672672
status = "disabled";
673673
#io-channel-cells = <1>;
@@ -683,7 +683,7 @@
683683
adc2: adc@42028100 {
684684
compatible = "st,stm32-adc";
685685
reg = <0x42028100 0x100>;
686-
clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
686+
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
687687
interrupts = <37 0>;
688688
status = "disabled";
689689
#io-channel-cells = <1>;
@@ -716,23 +716,23 @@
716716
ram-size = <1024>;
717717
maximum-speed = "full-speed";
718718
status = "disabled";
719-
clocks = <&rcc STM32_CLOCK(APB1_2, 21U)>,
719+
clocks = <&rcc STM32_CLOCK(APB1_2, 21)>,
720720
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
721721
phys = <&usb_fs_phy>;
722722
};
723723

724724
ucpd1: ucpd@4000dc00 {
725725
compatible = "st,stm32-ucpd";
726726
reg = <0x4000dc00 0x400>;
727-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
727+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
728728
interrupts = <106 0>;
729729
status = "disabled";
730730
};
731731

732732
fmc: fmc@44020000 {
733733
compatible = "st,stm32-fmc";
734734
reg = <0x44020000 0x400>;
735-
clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
735+
clocks = <&rcc STM32_CLOCK(AHB3, 0)>;
736736
status = "disabled";
737737
};
738738
};

‎dts/arm/st/l5/stm32l562.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
aes: aes@420c0000 {
1414
compatible = "st,stm32-aes";
1515
reg = <0x420c0000 0x400>;
16-
clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
16+
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
1717
resets = <&rctl STM32_RESET(AHB2, 16U)>;
1818
interrupts = <93 0>;
1919
status = "disabled";

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