Skip to content

Commit 7628ac7

Browse files
Mathieu Choplainkartben
Mathieu Choplain
authored and
kartben
committed
dts: arm: st: stm32l4: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
1 parent 0744927 commit 7628ac7

18 files changed

+112
-112
lines changed

‎dts/arm/st/l4/stm32l4.dtsi‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@
125125
compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
126126
reg = <0x40022000 0x400>;
127127
interrupts = <4 0>;
128-
clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
128+
clocks = <&rcc STM32_CLOCK(AHB1, 8)>;
129129

130130
#address-cells = <1>;
131131
#size-cells = <1>;
@@ -178,31 +178,31 @@
178178
gpio-controller;
179179
#gpio-cells = <2>;
180180
reg = <0x48000000 0x400>;
181-
clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
181+
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
182182
};
183183

184184
gpiob: gpio@48000400 {
185185
compatible = "st,stm32-gpio";
186186
gpio-controller;
187187
#gpio-cells = <2>;
188188
reg = <0x48000400 0x400>;
189-
clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
189+
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
190190
};
191191

192192
gpioc: gpio@48000800 {
193193
compatible = "st,stm32-gpio";
194194
gpio-controller;
195195
#gpio-cells = <2>;
196196
reg = <0x48000800 0x400>;
197-
clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
197+
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
198198
};
199199

200200
gpioh: gpio@48001c00 {
201201
compatible = "st,stm32-gpio";
202202
gpio-controller;
203203
#gpio-cells = <2>;
204204
reg = <0x48001c00 0x400>;
205-
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
205+
clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
206206
};
207207
};
208208

@@ -215,15 +215,15 @@
215215
wwdg: watchdog@40002c00 {
216216
compatible = "st,stm32-window-watchdog";
217217
reg = <0x40002C00 0x400>;
218-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
218+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
219219
interrupts = <0 7>;
220220
status = "disabled";
221221
};
222222

223223
usart1: serial@40013800 {
224224
compatible = "st,stm32-usart", "st,stm32-uart";
225225
reg = <0x40013800 0x400>;
226-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
226+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
227227
resets = <&rctl STM32_RESET(APB2, 14U)>;
228228
interrupts = <37 0>;
229229
status = "disabled";
@@ -232,7 +232,7 @@
232232
usart2: serial@40004400 {
233233
compatible = "st,stm32-usart", "st,stm32-uart";
234234
reg = <0x40004400 0x400>;
235-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
235+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
236236
resets = <&rctl STM32_RESET(APB1L, 17U)>;
237237
interrupts = <38 0>;
238238
status = "disabled";
@@ -241,7 +241,7 @@
241241
lpuart1: serial@40008000 {
242242
compatible = "st,stm32-lpuart", "st,stm32-uart";
243243
reg = <0x40008000 0x400>;
244-
clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
244+
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
245245
resets = <&rctl STM32_RESET(APB1H, 0U)>;
246246
interrupts = <70 0>;
247247
status = "disabled";
@@ -253,7 +253,7 @@
253253
#address-cells = <1>;
254254
#size-cells = <0>;
255255
reg = <0x40005400 0x400>;
256-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
256+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
257257
interrupts = <31 0>, <32 0>;
258258
interrupt-names = "event", "error";
259259
status = "disabled";
@@ -265,7 +265,7 @@
265265
#address-cells = <1>;
266266
#size-cells = <0>;
267267
reg = <0x40005c00 0x400>;
268-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
268+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
269269
interrupts = <72 0>, <73 0>;
270270
interrupt-names = "event", "error";
271271
status = "disabled";
@@ -277,7 +277,7 @@
277277
#size-cells = <0>;
278278
reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
279279
interrupts = <71 0>;
280-
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
280+
clocks = <&rcc STM32_CLOCK(AHB3, 8)>;
281281
status = "disabled";
282282
};
283283

@@ -287,7 +287,7 @@
287287
#size-cells = <0>;
288288
reg = <0x40013000 0x400>;
289289
interrupts = <35 5>;
290-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
290+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
291291
status = "disabled";
292292
};
293293

@@ -400,7 +400,7 @@
400400
compatible = "st,stm32-rtc";
401401
reg = <0x40002800 0x400>;
402402
interrupts = <41 0>;
403-
clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
403+
clocks = <&rcc STM32_CLOCK(APB1, 28)>;
404404
prescaler = <32768>;
405405
alarms-count = <2>;
406406
alrm-exti-line = <18>;
@@ -410,7 +410,7 @@
410410
adc1: adc@50040000 {
411411
compatible = "st,stm32-adc";
412412
reg = <0x50040000 0x100>;
413-
clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
413+
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
414414
interrupts = <18 0>;
415415
status = "disabled";
416416
#io-channel-cells = <1>;
@@ -426,7 +426,7 @@
426426
adc2: adc@50040100 {
427427
compatible = "st,stm32-adc";
428428
reg = <0x50040100 0x100>;
429-
clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
429+
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
430430
interrupts = <18 0>;
431431
status = "disabled";
432432
#io-channel-cells = <1>;
@@ -444,7 +444,7 @@
444444
#dma-cells = <3>;
445445
reg = <0x40020000 0x400>;
446446
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
447-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
447+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
448448
dma-requests = <7>;
449449
status = "disabled";
450450
};
@@ -454,14 +454,14 @@
454454
#dma-cells = <3>;
455455
reg = <0x40020400 0x400>;
456456
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
457-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
457+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
458458
dma-requests = <7>;
459459
status = "disabled";
460460
};
461461

462462
lptim1: timers@40007c00 {
463463
compatible = "st,stm32-lptim";
464-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
464+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
465465
#address-cells = <1>;
466466
#size-cells = <0>;
467467
reg = <0x40007c00 0x400>;
@@ -475,7 +475,7 @@
475475
#address-cells = <1>;
476476
#size-cells = <0>;
477477
reg = <0x40009400 0x400>;
478-
clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
478+
clocks = <&rcc STM32_CLOCK(APB1_2, 5)>;
479479
interrupts = <66 1>;
480480
interrupt-names = "wakeup";
481481
status = "disabled";
@@ -485,7 +485,7 @@
485485
compatible = "st,stm32-rng";
486486
reg = <0x50060800 0x400>;
487487
interrupts = <80 0>;
488-
clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
488+
clocks = <&rcc STM32_CLOCK(AHB2, 18)>,
489489
/* Following domain clock setting requires MSI
490490
* clock to be enabled with msi-range = <11>;
491491
*/

‎dts/arm/st/l4/stm32l412.dtsi‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222

2323

2424
rng: rng@50060800 {
25-
clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
25+
clocks = <&rcc STM32_CLOCK(AHB2, 18)>,
2626
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
2727
};
2828

@@ -35,7 +35,7 @@
3535
ram-size = <1024>;
3636
maximum-speed = "full-speed";
3737
phys = <&usb_fs_phy>;
38-
clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
38+
clocks = <&rcc STM32_CLOCK(APB1, 26)>,
3939
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
4040
status = "disabled";
4141
};
@@ -45,7 +45,7 @@
4545
#address-cells = <1>;
4646
#size-cells = <0>;
4747
reg = <0x40005800 0x400>;
48-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
48+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
4949
clock-frequency = <I2C_BITRATE_STANDARD>;
5050
interrupts = <33 0>, <34 0>;
5151
interrupt-names = "event", "error";
@@ -58,14 +58,14 @@
5858
#size-cells = <0>;
5959
reg = <0x40003800 0x400>;
6060
interrupts = <36 5>;
61-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
61+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
6262
status = "disabled";
6363
};
6464

6565
usart3: serial@40004800 {
6666
compatible = "st,stm32-usart", "st,stm32-uart";
6767
reg = <0x40004800 0x400>;
68-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
68+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
6969
resets = <&rctl STM32_RESET(APB1L, 18U)>;
7070
interrupts = <39 0>;
7171
status = "disabled";

‎dts/arm/st/l4/stm32l422.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
aes: aes@50060000 {
1414
compatible = "st,stm32l4-aes", "st,stm32-aes";
1515
reg = <0x50060000 0x400>;
16-
clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
16+
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
1717
resets = <&rctl STM32_RESET(AHB2, 16U)>;
1818
interrupts = <79 0>;
1919
interrupt-names = "aes";

‎dts/arm/st/l4/stm32l431.dtsi‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -25,23 +25,23 @@
2525
gpiod: gpio@48000c00 {
2626
compatible = "st,stm32-gpio";
2727
reg = <0x48000c00 0x400>;
28-
clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
28+
clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
2929
gpio-controller;
3030
#gpio-cells = <2>;
3131
};
3232

3333
gpioe: gpio@48001000 {
3434
compatible = "st,stm32-gpio";
3535
reg = <0x48001000 0x400>;
36-
clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36+
clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
3737
gpio-controller;
3838
#gpio-cells = <2>;
3939
};
4040

4141
};
4242

4343
rng: rng@50060800 {
44-
clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
44+
clocks = <&rcc STM32_CLOCK(AHB2, 18)>,
4545
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
4646
};
4747

@@ -50,7 +50,7 @@
5050
#address-cells = <1>;
5151
#size-cells = <0>;
5252
reg = <0x40005800 0x400>;
53-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
53+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
5454
clock-frequency = <I2C_BITRATE_STANDARD>;
5555
interrupts = <33 0>, <34 0>;
5656
interrupt-names = "event", "error";
@@ -62,7 +62,7 @@
6262
#address-cells = <1>;
6363
#size-cells = <0>;
6464
reg = <0x40003800 0x400>;
65-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
65+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
6666
interrupts = <36 5>;
6767
status = "disabled";
6868
};
@@ -72,15 +72,15 @@
7272
#address-cells = <1>;
7373
#size-cells = <0>;
7474
reg = <0x40003c00 0x400>;
75-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
75+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
7676
interrupts = <51 5>;
7777
status = "disabled";
7878
};
7979

8080
usart3: serial@40004800 {
8181
compatible = "st,stm32-usart", "st,stm32-uart";
8282
reg = <0x40004800 0x400>;
83-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
83+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
8484
resets = <&rctl STM32_RESET(APB1L, 18U)>;
8585
interrupts = <39 0>;
8686
status = "disabled";
@@ -106,7 +106,7 @@
106106
can1: can@40006400 {
107107
compatible = "st,stm32-bxcan";
108108
reg = <0x40006400 0x400>;
109-
clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
109+
clocks = <&rcc STM32_CLOCK(APB1, 25)>;
110110
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
111111
interrupt-names = "TX", "RX0", "RX1", "SCE";
112112
status = "disabled";
@@ -115,7 +115,7 @@
115115
sdmmc1: sdmmc@40012800 {
116116
compatible = "st,stm32-sdmmc";
117117
reg = <0x40012800 0x400>;
118-
clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
118+
clocks = <&rcc STM32_CLOCK(APB2, 10)>,
119119
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
120120
resets = <&rctl STM32_RESET(APB2, 10U)>;
121121
interrupts = <49 0>;
@@ -125,7 +125,7 @@
125125
dac1: dac@40007400 {
126126
compatible = "st,stm32-dac";
127127
reg = <0x40007400 0x400>;
128-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
128+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
129129
#io-channel-cells = <1>;
130130
status = "disabled";
131131
};

‎dts/arm/st/l4/stm32l432.dtsi‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
compatible = "st,stm32l432", "st,stm32l4", "simple-bus";
2222

2323
rng: rng@50060800 {
24-
clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
24+
clocks = <&rcc STM32_CLOCK(AHB2, 18)>,
2525
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
2626
};
2727

@@ -30,7 +30,7 @@
3030
#address-cells = <1>;
3131
#size-cells = <0>;
3232
reg = <0x40003c00 0x400>;
33-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
33+
clocks = <&rcc STM32_CLOCK(APB1, 15)>;
3434
interrupts = <51 5>;
3535
status = "disabled";
3636
};
@@ -57,7 +57,7 @@
5757
reg = <0x40006400 0x400>;
5858
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
5959
interrupt-names = "TX", "RX0", "RX1", "SCE";
60-
clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
60+
clocks = <&rcc STM32_CLOCK(APB1, 25)>; //RCC_APB1ENR1_CAN1EN
6161
status = "disabled";
6262
};
6363

@@ -70,15 +70,15 @@
7070
ram-size = <1024>;
7171
maximum-speed = "full-speed";
7272
phys = <&usb_fs_phy>;
73-
clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
73+
clocks = <&rcc STM32_CLOCK(APB1, 26)>,
7474
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
7575
status = "disabled";
7676
};
7777

7878
dac1: dac@40007400 {
7979
compatible = "st,stm32-dac";
8080
reg = <0x40007400 0x400>;
81-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
81+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
8282
status = "disabled";
8383
#io-channel-cells = <1>;
8484
};

0 commit comments

Comments
 (0)