devicetree: format files in dts/riscv/starfive

Applying dts-linter results for files in

dts/riscv/starfive

Signed-off-by: Kyle Micallef Bonnici <[email protected]>

Author: kylebonnici

dts/riscv/starfive/jh7110-visionfive-v2.dtsi

@@ -25,6 +25,7 @@
 			reg = <0>;
 			riscv,isa = "rv64imac_zicsr_zifencei";
 			status = "okay";
+
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
@@ -50,6 +51,7 @@
 			reg = <0x1>;
 			riscv,isa = "rv64imafdcg";
 			tlb-spilt;
+
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#interrupt-cells = <1>;
@@ -75,6 +77,7 @@
 			reg = <0x2>;
 			riscv,isa = "rv64imafdcg";
 			tlb-split;
+
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#interrupt-cells = <1>;
@@ -100,6 +103,7 @@
 			reg = <0x3>;
 			riscv,isa = "rv64imafdcg";
 			tlb-split;
+
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#interrupt-cells = <1>;
@@ -125,6 +129,7 @@
 			reg = <0x4>;
 			riscv,isa = "rv64imafdcg";
 			tlb-split;
+
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#interrupt-cells = <1>;
@@ -148,20 +153,20 @@
 		clint: clint@2000000 {
 			compatible = "sifive,clint0";
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-						&cpu1_intc 3 &cpu1_intc 7
-						&cpu2_intc 3 &cpu2_intc 7
-						&cpu3_intc 3 &cpu3_intc 7
-						&cpu4_intc 3 &cpu4_intc 7>;
+					       &cpu1_intc 3 &cpu1_intc 7
+					       &cpu2_intc 3 &cpu2_intc 7
+					       &cpu3_intc 3 &cpu3_intc 7
+					       &cpu4_intc 3 &cpu4_intc 7>;
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
 		mtimer: timer@200bff8 {
 			compatible = "riscv,machine-timer";
 			interrupts-extended = <&cpu0_intc 7
-						&cpu1_intc 7
-						&cpu2_intc 7
-						&cpu3_intc 7
-						&cpu4_intc 7>;
+					       &cpu1_intc 7
+					       &cpu2_intc 7
+					       &cpu3_intc 7
+					       &cpu4_intc 7>;
 			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
 			reg-names = "mtime", "mtimecmp";
 		};
@@ -184,10 +189,10 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			interrupts-extended = <&cpu0_intc 11>,
-						<&cpu1_intc 11>, <&cpu1_intc 9>,
-						<&cpu2_intc 11>, <&cpu2_intc 9>,
-						<&cpu3_intc 11>, <&cpu3_intc 9>,
-						<&cpu4_intc 11>, <&cpu4_intc 9>;
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>;
 			reg = <0x0 0x0c000000 0x0 0x04000000>;
 			riscv,max-priority = <7>;
 			riscv,ndev = <52>;

dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi

@@ -17,6 +17,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "starfive,fu74-g000";
+
 		cpu@0 {
 			clock-frequency = <0>;
 			compatible = "starfive,rocket0", "riscv";
@@ -38,6 +39,7 @@
 			starfive,itim = <&itim0>;
 			status = "okay";
 			tlb-split;
+
 			cpu0intctrl: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#address-cells = <0>;
@@ -67,6 +69,7 @@
 			starfive,itim = <&itim1>;
 			status = "okay";
 			tlb-split;
+
 			cpu1intctrl: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				#address-cells = <0>;
@@ -76,7 +79,7 @@
 		};
 	};
 
-	ram0:memory@80000000 {
+	ram0: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x2 0x0>;
 	};
@@ -134,7 +137,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9
-					       &cpu1intctrl 11 &cpu1intctrl 9 >;
+					       &cpu1intctrl 11 &cpu1intctrl 9>;
 			reg = <0x0 0x0c000000 0x0 0x04000000>;
 			riscv,max-priority = <7>;
 			riscv,ndev = <127>;
@@ -173,7 +176,7 @@
 			reg = <0x0 0x11880000 0x0 0x10000>;
 			reg-shift = <2>;
 			clocks = <&hs_uartclk>, <&apb1clk>;
-			clock-names = "baudclk","apb_pclk";
+			clock-names = "baudclk", "apb_pclk";
 			clock-frequency = <74250000>;
 			current-speed = <115200>;
 			status = "disabled";