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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32wl: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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‎dts/arm/st/wl/stm32wl.dtsi‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -170,37 +170,37 @@
170170
gpio-controller;
171171
#gpio-cells = <2>;
172172
reg = <0x48000000 0x400>;
173-
clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
173+
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
174174
};
175175

176176
gpiob: gpio@48000400 {
177177
compatible = "st,stm32-gpio";
178178
gpio-controller;
179179
#gpio-cells = <2>;
180180
reg = <0x48000400 0x400>;
181-
clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
181+
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
182182
};
183183

184184
gpioc: gpio@48000800 {
185185
compatible = "st,stm32-gpio";
186186
gpio-controller;
187187
#gpio-cells = <2>;
188188
reg = <0x48000800 0x400>;
189-
clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
189+
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
190190
};
191191

192192
gpioh: gpio@48001c00 {
193193
compatible = "st,stm32-gpio";
194194
gpio-controller;
195195
#gpio-cells = <2>;
196196
reg = <0x48001c00 0x400>;
197-
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
197+
clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
198198
};
199199
};
200200

201201
lptim1: timers@40007c00 {
202202
compatible = "st,stm32-lptim";
203-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
203+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
204204
#address-cells = <1>;
205205
#size-cells = <0>;
206206
reg = <0x40007c00 0x400>;
@@ -213,7 +213,7 @@
213213
compatible = "st,stm32-rtc";
214214
reg = <0x40002800 0x400>;
215215
interrupts = <42 0>;
216-
clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
216+
clocks = <&rcc STM32_CLOCK(APB1, 10)>;
217217
prescaler = <32768>;
218218
alarms-count = <2>;
219219
alrm-exti-line = <17>;
@@ -241,15 +241,15 @@
241241
wwdg: watchdog@40002c00 {
242242
compatible = "st,stm32-window-watchdog";
243243
reg = <0x40002C00 0x400>;
244-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
244+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
245245
interrupts = <0 7>;
246246
status = "disabled";
247247
};
248248

249249
usart1: serial@40013800 {
250250
compatible = "st,stm32-usart", "st,stm32-uart";
251251
reg = <0x40013800 0x400>;
252-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
252+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
253253
resets = <&rctl STM32_RESET(APB2, 14U)>;
254254
interrupts = <36 0>;
255255
status = "disabled";
@@ -258,7 +258,7 @@
258258
usart2: serial@40004400 {
259259
compatible = "st,stm32-usart", "st,stm32-uart";
260260
reg = <0x40004400 0x400>;
261-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
261+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
262262
resets = <&rctl STM32_RESET(APB1L, 17U)>;
263263
interrupts = <37 0>;
264264
status = "disabled";
@@ -267,7 +267,7 @@
267267
lpuart1: serial@40008000 {
268268
compatible = "st,stm32-lpuart", "st,stm32-uart";
269269
reg = <0x40008000 0x400>;
270-
clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
270+
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
271271
resets = <&rctl STM32_RESET(APB1H, 0U)>;
272272
interrupts = <38 0>;
273273
wakeup-line = <28>;
@@ -280,7 +280,7 @@
280280
#address-cells = <1>;
281281
#size-cells = <0>;
282282
reg = <0x40005400 0x400>;
283-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
283+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
284284
interrupts = <30 0>, <31 0>;
285285
interrupt-names = "event", "error";
286286
status = "disabled";
@@ -292,7 +292,7 @@
292292
#address-cells = <1>;
293293
#size-cells = <0>;
294294
reg = <0x40005800 0x400>;
295-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
295+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
296296
interrupts = <32 0>, <33 0>;
297297
interrupt-names = "event", "error";
298298
status = "disabled";
@@ -304,7 +304,7 @@
304304
#address-cells = <1>;
305305
#size-cells = <0>;
306306
reg = <0x40005c00 0x400>;
307-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
307+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
308308
interrupts = <48 0>, <49 0>;
309309
interrupt-names = "event", "error";
310310
status = "disabled";
@@ -316,7 +316,7 @@
316316
#size-cells = <0>;
317317
reg = <0x40013000 0x400>;
318318
interrupts = <34 5>;
319-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
319+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
320320
status = "disabled";
321321
};
322322

@@ -326,7 +326,7 @@
326326
#size-cells = <0>;
327327
reg = <0x40003800 0x400>;
328328
interrupts = <35 5>;
329-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
329+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
330330
status = "disabled";
331331
};
332332

@@ -336,7 +336,7 @@
336336
#size-cells = <0>;
337337
reg = <0x58010000 0x400>;
338338
interrupts = <44 5>;
339-
clocks = <&rcc STM32_CLOCK(APB3, 0U)>;
339+
clocks = <&rcc STM32_CLOCK(APB3, 0)>;
340340
status = "disabled";
341341
use-subghzspi-nss;
342342

@@ -352,7 +352,7 @@
352352
adc1: adc@40012400 {
353353
compatible = "st,stm32-adc";
354354
reg = <0x40012400 0x400>;
355-
clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
355+
clocks = <&rcc STM32_CLOCK(APB2, 9)>;
356356
interrupts = <18 0>;
357357
status = "disabled";
358358
#io-channel-cells = <1>;
@@ -369,7 +369,7 @@
369369
dac1: dac@40007400 {
370370
compatible = "st,stm32-dac";
371371
reg = <0x40007400 0x400>;
372-
clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
372+
clocks = <&rcc STM32_CLOCK(APB1, 29)>;
373373
status = "disabled";
374374
#io-channel-cells = <1>;
375375
};
@@ -464,7 +464,7 @@
464464
aes: aes@58001800 {
465465
compatible = "st,stm32-aes";
466466
reg = <0x58001800 0x400>;
467-
clocks = <&rcc STM32_CLOCK(AHB3, 17U)>;
467+
clocks = <&rcc STM32_CLOCK(AHB3, 17)>;
468468
resets = <&rctl STM32_RESET(AHB3, 16U)>;
469469
interrupts = <51 0>;
470470
status = "disabled";
@@ -474,7 +474,7 @@
474474
compatible = "st,stm32-rng";
475475
reg = <0x58001000 0x400>;
476476
interrupts = <52 0>;
477-
clocks = <&rcc STM32_CLOCK(AHB3, 18U)>;
477+
clocks = <&rcc STM32_CLOCK(AHB3, 18)>;
478478
health-test-magic = <0x17590abc>;
479479
health-test-config = <0xaa74>;
480480
status = "disabled";
@@ -485,7 +485,7 @@
485485
#dma-cells = <3>;
486486
reg = <0x40020000 0x400>;
487487
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
488-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
488+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
489489
dma-requests = <7>;
490490
dma-offset = <0>;
491491
status = "disabled";
@@ -496,7 +496,7 @@
496496
#dma-cells = <3>;
497497
reg = <0x40020400 0x400>;
498498
interrupts = <54 0 55 0 56 0 57 0 58 0 59 0 60 0>;
499-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
499+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
500500
dma-requests = <7>;
501501
dma-offset = <7>;
502502
status = "disabled";
@@ -507,7 +507,7 @@
507507
#dma-cells = <3>;
508508
reg = <0x40020800 0x400>;
509509
interrupts = <61 0>;
510-
clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
510+
clocks = <&rcc STM32_CLOCK(AHB1, 2)>;
511511
dma-channels = <14>;
512512
dma-generators = <4>;
513513
dma-requests= <38>;

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