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soc: infineon: psc3: Adding folder structure for PSC3 series
Adding kconfig, and other soc files for PSOC Control C3 devices Signed-off-by: Sreeram Tatapudi <[email protected]>
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‎soc/infineon/cat1b/psc3/CMakeLists.txt

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# Copyright (c) 2025 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_include_directories(.)
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# CAT1B family defines
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zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B COMPONENT_CAT1B)
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zephyr_compile_definitions(COMPONENT_CM33)
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zephyr_compile_definitions(CORE_NAME_CM33_0)
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zephyr_compile_definitions_ifdef(CONFIG_TRUSTED_EXECUTION_SECURE COMPONENT_SECURE_DEVICE)
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zephyr_compile_definitions(FLASH_BOOT)
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zephyr_compile_definitions(CY_PDL_FLASH_BOOT)
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zephyr_compile_definitions(NORMAL_PROVISIONED_LCS)
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zephyr_compile_definitions(USER_FLASH_S_SIZE=0x10000)
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zephyr_compile_definitions(USER_SRAM_S_SIZE=0x4000)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/infineon/cat1b/psc3/Kconfig

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# copyright (c) (2016-2025), Cypress Semiconductor Corporation
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# (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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config SOC_SERIES_PSC3
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select ARM
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select ARM_TRUSTZONE_M
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select ARCH_HAS_TRUSTED_EXECUTION
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select BUILD_OUTPUT_HEX
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select BUILD_OUTPUT_BIN
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select CPU_CORTEX_M_HAS_CMSE
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select SOC_EARLY_INIT_HOOK
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select CPU_CORTEX_M33

‎soc/infineon/cat1b/psc3/Kconfig.defconfig

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# copyright (c) (2016-2025), Cypress Semiconductor Corporation
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# (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Infineon PSC3 based MCU default configuration
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if SOC_SERIES_PSC3
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config NUM_IRQS
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default 140
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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# add additional die specific params
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endif # SOC_SERIES_PSC3

‎soc/infineon/cat1b/psc3/Kconfig.soc

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# copyright (c) (2016-2025), Cypress Semiconductor Corporation
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# (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Infineon PSC3 series MCUs
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config SOC_SERIES_PSC3
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bool
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config SOC_SERIES
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default "psc3" if SOC_SERIES_PSC3
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config SOC_DIE_PSC3M5
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bool
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select SOC_FAMILY_INFINEON_CAT1B
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config SOC_DIE_PSC3P5
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bool
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select SOC_FAMILY_INFINEON_CAT1B
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config SOC_DIE_PSC3P2
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bool
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select SOC_FAMILY_INFINEON_CAT1B
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config SOC_DIE_PSC3M3
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bool
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select SOC_FAMILY_INFINEON_CAT1B
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# SOC Packages for Infineon PSC3 series MCUs
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config SOC_PACKAGE_PSC3_E_LQFP_80
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bool
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config SOC_PACKAGE_PSC3_E_LQFP_64
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bool
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config SOC_PACKAGE_PSC3_VQFN_64
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bool
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config SOC_PACKAGE_PSC3_VQFN_48
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bool
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config SOC_PACKAGE_PSC3_E_LQFP_48
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bool
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# Infineon PSC3 series MPNs
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config SOC_PSC3M5FDS2AFQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_80
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5FDS2LGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5FDS2ACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5FDS2LHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5FDS2ABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5EDAFQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_80
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5EDLGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5EDACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5EDLHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3M5EDABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M5
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config SOC_PSC3P5EDLGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5FDS2LGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5EDACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5FDS2ACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5EDLHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5FDS2LHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5EDABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P5FDS2ABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P5
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config SOC_PSC3P2EDLGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3P2FDS2LGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3M3EDLGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3M3FDS2LGQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3P2EDACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3P2FDS2ACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3M3EDACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3M3FDS2ACQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3P2EDLHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3P2FDS2LHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3M3EDLHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3M3FDS2LHQ1
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bool
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select SOC_PACKAGE_PSC3_VQFN_64
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3P2EDABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3P2FDS2ABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3P2
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config SOC_PSC3M3EDABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC_PSC3M3FDS2ABQ1
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bool
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select SOC_PACKAGE_PSC3_E_LQFP_48
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select SOC_SERIES_PSC3
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select SOC_DIE_PSC3M3
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config SOC
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default "psc3m5fds2afq1" if SOC_PSC3M5FDS2AFQ1
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default "psc3m5fds2lgq1" if SOC_PSC3M5FDS2LGQ1
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default "psc3m5fds2acq1" if SOC_PSC3M5FDS2ACQ1
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default "psc3m5fds2lhq1" if SOC_PSC3M5FDS2LHQ1
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default "psc3m5fds2abq1" if SOC_PSC3M5FDS2ABQ1
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default "psc3m5edafq1" if SOC_PSC3M5EDAFQ1
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default "psc3m5edlgq1" if SOC_PSC3M5EDLGQ1
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default "psc3m5edacq1" if SOC_PSC3M5EDACQ1
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default "psc3m5edlhq1" if SOC_PSC3M5EDLHQ1
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default "psc3m5edabq1" if SOC_PSC3M5EDABQ1
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default "psc3p5edlgq1" if SOC_PSC3P5EDLGQ1
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default "psc3p5fds2lgq1" if SOC_PSC3P5FDS2LGQ1
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default "psc3p5edacq1" if SOC_PSC3P5EDACQ1
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default "psc3p5fds2acq1" if SOC_PSC3P5FDS2ACQ1
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default "psc3p5edlhq1" if SOC_PSC3P5EDLHQ1
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default "psc3p5fds2lhq1" if SOC_PSC3P5FDS2LHQ1
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default "psc3p5edabq1" if SOC_PSC3P5EDABQ1
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default "psc3p5fds2abq1" if SOC_PSC3P5FDS2ABQ1
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default "psc3p2edlgq1" if SOC_PSC3P2EDLGQ1
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default "psc3p2fds2lgq1" if SOC_PSC3P2FDS2LGQ1
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default "psc3m3edlgq1" if SOC_PSC3M3EDLGQ1
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default "psc3m3fds2lgq1" if SOC_PSC3M3FDS2LGQ1
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default "psc3p2edacq1" if SOC_PSC3P2EDACQ1
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default "psc3p2fds2acq1" if SOC_PSC3P2FDS2ACQ1
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default "psc3m3edacq1" if SOC_PSC3M3EDACQ1
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default "psc3m3fds2acq1" if SOC_PSC3M3FDS2ACQ1
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default "psc3p2edlhq1" if SOC_PSC3P2EDLHQ1
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default "psc3p2fds2lhq1" if SOC_PSC3P2FDS2LHQ1
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default "psc3m3edlhq1" if SOC_PSC3M3EDLHQ1
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default "psc3m3fds2lhq1" if SOC_PSC3M3FDS2LHQ1
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default "psc3p2edabq1" if SOC_PSC3P2EDABQ1
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default "psc3p2fds2abq1" if SOC_PSC3P2FDS2ABQ1
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default "psc3m3edabq1" if SOC_PSC3M3EDABQ1
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default "psc3m3fds2abq1" if SOC_PSC3M3FDS2ABQ1

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