riscv: Introduce qemu_riscv32e board.

To support and test RV32E.

Signed-off-by: Carlo Caione <[email protected]>

Author: carlocaione

boards/riscv/qemu_riscv32e/Kconfig.board

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Carlo Caione <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV32E
+	bool "QEMU RISCV32E target"
+	depends on SOC_RISCV_VIRT
+	select QEMU_TARGET
+	select RISCV_ISA_RV32E

boards/riscv/qemu_riscv32e/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2022 Carlo Caione <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config BOARD
+	default "qemu_riscv32e" if BOARD_QEMU_RISCV32E
+
+# Use thread local storage by default so that
+# this feature gets more CI coverage.
+config THREAD_LOCAL_STORAGE
+	default y

boards/riscv/qemu_riscv32e/board.cmake

@@ -0,0 +1,16 @@
+# Copyright (c) 2022 Carlo Caione <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS qemu)
+
+set(QEMU_binary_suffix riscv32)
+set(QEMU_CPU_TYPE_${ARCH} riscv32)
+
+set(QEMU_FLAGS_${ARCH}
+  -nographic
+  -machine virt
+  -bios none
+  -m 256
+  )
+
+board_set_debugger_ifnset(qemu)

boards/riscv/qemu_riscv32e/doc/index.rst

@@ -0,0 +1,62 @@
+.. _qemu_riscv32e:
+
+RISCV32E Emulation (QEMU)
+#########################
+
+Overview
+********
+
+The RISCV32E QEMU board configuration is used to emulate the RISCV32 (RV32E) architecture.
+
+.. figure:: qemu_riscv32.png
+   :width: 600px
+   :align: center
+   :alt: Qemu
+
+   Qemu (Credit: qemu.org)
+
+Programming and Debugging
+*************************
+
+Applications for the ``qemu_riscv32e`` board configuration can be built and run in
+the usual way for emulated boards (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+While this board is emulated and you can't "flash" it, you can use this
+configuration to run basic Zephyr applications and kernel tests in the QEMU
+emulated environment. For example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: qemu_riscv32e
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it using
+QEMU, and display the following console output:
+
+.. code-block:: console
+
+        *** Booting Zephyr OS build v3.1.0-rc1-59-g0d66cc1f6645  ***
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+        thread_a: Hello World from cpu 0 on qemu_riscv32e!
+        thread_b: Hello World from cpu 0 on qemu_riscv32e!
+
+Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.

boards/riscv/qemu_riscv32e/doc/qemu_riscv32.png

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2022 Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+/dts-v1/;
+
+#include <virt.dtsi>
+
+/ {
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &ram0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

boards/riscv/qemu_riscv32e/qemu_riscv32e.dts

@@ -0,0 +1,15 @@
+identifier: qemu_riscv32e
+name: QEMU Emulation for RISC-V (RV32E) 32-bit
+type: qemu
+simulation: qemu
+arch: riscv32
+toolchain:
+  - zephyr
+  - xtools
+supported:
+  - netif
+testing:
+  default: true
+  ignore_tags:
+    - net
+    - bluetooth

boards/riscv/qemu_riscv32e/qemu_riscv32e.yaml

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_RISCV_VIRT=y
+CONFIG_SOC_RISCV_VIRT=y
+CONFIG_BOARD_QEMU_RISCV32E=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_PLIC=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_STACK_SENTINEL=y
+CONFIG_QEMU_ICOUNT_SHIFT=6
+CONFIG_XIP=n
+CONFIG_RISCV_PMP=y