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| 1 | +/* |
| 2 | + * Copyright (c) 2013-2014 Wind River Systems, Inc. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +/** |
| 8 | + * @file |
| 9 | + * @brief Full C support initialization |
| 10 | + * |
| 11 | + * |
| 12 | + * Initialization of full C support: zero the .bss, copy the .data if XIP, |
| 13 | + * call z_cstart(). |
| 14 | + * |
| 15 | + * Stack is available in this module, but not the global data/bss until their |
| 16 | + * initialization is performed. |
| 17 | + */ |
| 18 | + |
| 19 | +#include <zephyr/kernel.h> |
| 20 | +#include <kernel_internal.h> |
| 21 | +#include <zephyr/linker/linker-defs.h> |
| 22 | +#include <zephyr/sys/barrier.h> |
| 23 | +#include <zephyr/arch/arm/cortex_a_r/lib_helpers.h> |
| 24 | + |
| 25 | +#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) |
| 26 | +#include <cortex_a_r/stack.h> |
| 27 | +#endif |
| 28 | + |
| 29 | +#if defined(__GNUC__) |
| 30 | +/* |
| 31 | + * GCC can detect if memcpy is passed a NULL argument, however one of |
| 32 | + * the cases of relocate_vector_table() it is valid to pass NULL, so we |
| 33 | + * suppress the warning for this case. We need to do this before |
| 34 | + * string.h is included to get the declaration of memcpy. |
| 35 | + */ |
| 36 | +#pragma GCC diagnostic push |
| 37 | +#pragma GCC diagnostic ignored "-Wnonnull" |
| 38 | +#endif |
| 39 | + |
| 40 | +#include <string.h> |
| 41 | + |
| 42 | +#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) |
| 43 | +Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) |
| 44 | +void *_vector_table_pointer; |
| 45 | +#endif |
| 46 | + |
| 47 | +#if defined(CONFIG_AARCH32_ARMV8_R) |
| 48 | + |
| 49 | +#define VECTOR_ADDRESS ((uintptr_t)_vector_start) |
| 50 | + |
| 51 | +static inline void relocate_vector_table(void) |
| 52 | +{ |
| 53 | + write_sctlr(read_sctlr() & ~HIVECS); |
| 54 | + write_vbar(VECTOR_ADDRESS & VBAR_MASK); |
| 55 | + barrier_isync_fence_full(); |
| 56 | +} |
| 57 | + |
| 58 | +#else |
| 59 | +#define VECTOR_ADDRESS 0 |
| 60 | + |
| 61 | +void __weak relocate_vector_table(void) |
| 62 | +{ |
| 63 | +#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ |
| 64 | + !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) |
| 65 | + write_sctlr(read_sctlr() & ~HIVECS); |
| 66 | + size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; |
| 67 | + (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); |
| 68 | +#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) |
| 69 | + _vector_table_pointer = _vector_start; |
| 70 | +#endif |
| 71 | +} |
| 72 | + |
| 73 | +#if defined(__GNUC__) |
| 74 | +#pragma GCC diagnostic pop |
| 75 | +#endif |
| 76 | + |
| 77 | +#endif /* CONFIG_AARCH32_ARMV8_R */ |
| 78 | + |
| 79 | +#if defined(CONFIG_CPU_HAS_FPU) |
| 80 | + |
| 81 | +static inline void z_arm_floating_point_init(void) |
| 82 | +{ |
| 83 | +#if defined(CONFIG_FPU) |
| 84 | + uint32_t reg_val = 0; |
| 85 | + |
| 86 | + /* |
| 87 | + * CPACR : Coprocessor Access Control Register -> CP15 1/0/2 |
| 88 | + * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, |
| 89 | + * chap. B4.1.40 |
| 90 | + * |
| 91 | + * Must be accessed in >= PL1! |
| 92 | + * [23..22] = CP11 access control bits, |
| 93 | + * [21..20] = CP10 access control bits. |
| 94 | + * 11b = Full access as defined for the respective CP, |
| 95 | + * 10b = UNDEFINED, |
| 96 | + * 01b = Access at PL1 only, |
| 97 | + * 00b = No access. |
| 98 | + */ |
| 99 | + reg_val = __get_CPACR(); |
| 100 | + /* Enable PL1 access to CP10, CP11 */ |
| 101 | + reg_val |= (CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA)); |
| 102 | + __set_CPACR(reg_val); |
| 103 | + barrier_isync_fence_full(); |
| 104 | + |
| 105 | +#if !defined(CONFIG_FPU_SHARING) |
| 106 | + /* |
| 107 | + * FPEXC: Floating-Point Exception Control register |
| 108 | + * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, |
| 109 | + * chap. B6.1.38 |
| 110 | + * |
| 111 | + * Must be accessed in >= PL1! |
| 112 | + * [31] EX bit = determines which registers comprise the current state |
| 113 | + * of the FPU. The effects of setting this bit to 1 are |
| 114 | + * subarchitecture defined. If EX=0, the following |
| 115 | + * registers contain the complete current state |
| 116 | + * information of the FPU and must therefore be saved |
| 117 | + * during a context switch: |
| 118 | + * * D0-D15 |
| 119 | + * * D16-D31 if implemented |
| 120 | + * * FPSCR |
| 121 | + * * FPEXC. |
| 122 | + * [30] EN bit = Advanced SIMD/Floating Point Extensions enable bit. |
| 123 | + * [29..00] = Subarchitecture defined -> not relevant here. |
| 124 | + */ |
| 125 | + __set_FPEXC(FPEXC_EN); |
| 126 | +#endif |
| 127 | +#endif |
| 128 | +} |
| 129 | + |
| 130 | +#endif /* CONFIG_CPU_HAS_FPU */ |
| 131 | + |
| 132 | +extern FUNC_NORETURN void z_cstart(void); |
| 133 | + |
| 134 | +/** |
| 135 | + * |
| 136 | + * @brief Prepare to and run C code |
| 137 | + * |
| 138 | + * This routine prepares for the execution of and runs C code. |
| 139 | + * |
| 140 | + */ |
| 141 | +void z_arm_prep_c(void) |
| 142 | +{ |
| 143 | + relocate_vector_table(); |
| 144 | +#if defined(CONFIG_CPU_HAS_FPU) |
| 145 | + z_arm_floating_point_init(); |
| 146 | +#endif |
| 147 | + z_bss_zero(); |
| 148 | + z_data_copy(); |
| 149 | +#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS)) |
| 150 | + z_arm_init_stacks(); |
| 151 | +#endif |
| 152 | + z_arm_interrupt_init(); |
| 153 | + z_cstart(); |
| 154 | + CODE_UNREACHABLE; |
| 155 | +} |
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