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drivers: use fracn in clock stm32h7 driver
use fracn value if defined for each PLL 1, 2 and 3 based on stm32u5 code Signed-off-by: Nathan Olff <[email protected]>
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drivers/clock_control/clock_stm32_ll_h7.c

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -800,8 +800,11 @@ static int set_up_plls(void)
800800

801801
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
802802

803-
/* FRACN disable DIVP,DIVQ,DIVR enable*/
804803
LL_RCC_PLL1FRACN_Disable();
804+
if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
805+
LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
806+
LL_RCC_PLL1FRACN_Enable();
807+
}
805808

806809
if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
807810
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
@@ -846,6 +849,10 @@ static int set_up_plls(void)
846849
LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
847850

848851
LL_RCC_PLL2FRACN_Disable();
852+
if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {
853+
LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE);
854+
LL_RCC_PLL2FRACN_Enable();
855+
}
849856

850857
if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
851858
LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
@@ -896,6 +903,10 @@ static int set_up_plls(void)
896903
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
897904

898905
LL_RCC_PLL3FRACN_Disable();
906+
if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {
907+
LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE);
908+
LL_RCC_PLL3FRACN_Enable();
909+
}
899910

900911
if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
901912
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);

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