drivers: clock: stm32: use logical AND in preproc check

Replace bitwise AND (&) by logical AND (&&) within
preprocessor if statements in clock_stm32_ll_common.c

Signed-off-by: Alain Volmat <[email protected]>

Author: Alain Volmat

drivers/clock_control/clock_stm32_ll_common.c

@@ -484,47 +484,47 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 	case STM32_SRC_SYSCLK:
 		*rate = SystemCoreClock * STM32_CORE_PRESCALER;
 		break;
-#if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL)
+#if defined(STM32_SRC_PLLCLK) && defined(STM32_SYSCLK_SRC_PLL)
 	case STM32_SRC_PLLCLK:
 		if (get_pllout_frequency() == 0) {
 			return -EIO;
 		}
 		*rate = get_pllout_frequency();
 		break;
 #endif
-#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED
 	case STM32_SRC_PLL_P:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_P_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
+#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED
 	case STM32_SRC_PLL_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_Q_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED
+#if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED
 	case STM32_SRC_PLL_R:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_R_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_Q_ENABLED & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_Q) && STM32_PLLI2S_Q_ENABLED && STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,
 					      STM32_PLLI2S_N_MULTIPLIER,
 					      STM32_PLLI2S_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLI2S_Q */
-#if defined(STM32_SRC_PLLI2S_R) & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_R) && STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_R:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,
@@ -576,56 +576,56 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 		*rate /= STM32_PLLSAI_DIVR_DIVISOR;
 		break;
 #endif /* STM32_SRC_PLLSAI_DIVR */
-#if defined(STM32_SRC_PLLSAI1_P) & STM32_PLLSAI1_P_ENABLED
+#if defined(STM32_SRC_PLLSAI1_P) && STM32_PLLSAI1_P_ENABLED
 	case STM32_SRC_PLLSAI1_P:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_P_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_P */
-#if defined(STM32_SRC_PLLSAI1_Q) & STM32_PLLSAI1_Q_ENABLED
+#if defined(STM32_SRC_PLLSAI1_Q) && STM32_PLLSAI1_Q_ENABLED
 	case STM32_SRC_PLLSAI1_Q:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_Q */
-#if defined(STM32_SRC_PLLSAI1_R) & STM32_PLLSAI1_R_ENABLED
+#if defined(STM32_SRC_PLLSAI1_R) && STM32_PLLSAI1_R_ENABLED
 	case STM32_SRC_PLLSAI1_R:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_R */
-#if defined(STM32_SRC_PLLSAI2_P) & STM32_PLLSAI2_P_ENABLED
+#if defined(STM32_SRC_PLLSAI2_P) && STM32_PLLSAI2_P_ENABLED
 	case STM32_SRC_PLLSAI2_P:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_P_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_P */
-#if defined(STM32_SRC_PLLSAI2_Q) & STM32_PLLSAI2_Q_ENABLED
+#if defined(STM32_SRC_PLLSAI2_Q) && STM32_PLLSAI2_Q_ENABLED
 	case STM32_SRC_PLLSAI2_Q:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_Q */
-#if defined(STM32_SRC_PLLSAI2_R) & STM32_PLLSAI2_R_ENABLED
+#if defined(STM32_SRC_PLLSAI2_R) && STM32_PLLSAI2_R_ENABLED
 	case STM32_SRC_PLLSAI2_R:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_R */
-#if defined(STM32_SRC_PLLSAI2_DIVR) & STM32_PLLSAI2_R_ENABLED & STM32_PLLSAI2_DIVR_ENABLED \
-	& defined(STM32_PLLSAI2_DIVR_DIVISOR)
+#if defined(STM32_SRC_PLLSAI2_DIVR) && STM32_PLLSAI2_R_ENABLED && STM32_PLLSAI2_DIVR_ENABLED && \
+	defined(STM32_PLLSAI2_DIVR_DIVISOR)
 	case STM32_SRC_PLLSAI2_DIVR:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
@@ -812,11 +812,11 @@ static void set_up_plls(void)
 
 #if defined(STM32_PLL_ENABLED)
 
-#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED
 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
 	RCC_PLLP_ENABLE();
 #endif
-#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
+#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED
 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
 	RCC_PLLQ_ENABLE();
 #endif