driver: clock: stm32 clock control supports ahb_prescaler

This constraint on the AHB prescaler is removed.
The ahb-prescaler is allow from 1-512.
For stm32 common and stm32U5 devices.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

drivers/clock_control/clock_stm32_ll_common.c

@@ -64,17 +64,6 @@
 #define STM32WL_DUAL_CORE
 #endif
 
-#if STM32_AHB_PRESCALER > 1
-/*
- * AHB prescaler allows to set a HCLK frequency (feeding cortex systick)
- * lower than SYSCLK frequency (actual core frequency).
- * Though, zephyr doesn't make a difference today between these two clocks.
- * So, changing this prescaler is not allowed until it is made possible to
- * use them independently in zephyr clock subsystem.
- */
-#error "AHB prescaler can't be higher than 1"
-#endif
-
 /**
  * @brief fill in AHB/APB buses configuration structure
  */

drivers/clock_control/clock_stm32_ll_u5.c

@@ -30,18 +30,6 @@
 #define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
 #define apb3_prescaler(v) z_apb3_prescaler(v)
 
-
-#if STM32_AHB_PRESCALER > 1
-/*
- * AHB prescaler allows to set a HCLK frequency (feeding cortex systick)
- * lower than SYSCLK frequency (actual core frequency).
- * Though, zephyr doesn't make a difference today between these two clocks.
- * So, changing this prescaler is not allowed until it is made possible to
- * use them independently in zephyr clock subsystem.
- */
-#error "AHB prescaler can't be higher than 1"
-#endif
-
 #if STM32_SYSCLK_SRC_PLL
 
 /**