boards: nxp: mcx: update FlexCAN clock configuration

Update FlexCAN clock configuration across NXP MCXN family boards to use
PLL0 as clock source with a divider of 3 instead of FRO_HF with divider
of 1.
The new configuration provides FlexCAN peripherals by using the PLL0
output (150MHz) divided by 3 to achieve 50MHz, replace previous 48MHz
FRO_HF.

Signed-off-by: William Tang <[email protected]>

Author: william-tang914

boards/nxp/frdm_mcxn236/board.c

@@ -211,8 +211,8 @@ void board_early_init_hook(void)
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1))
-	CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 1U);
-	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN1);
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 3U);
+	CLOCK_AttachClk(kPLL0_to_FLEXCAN1);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref))

boards/nxp/frdm_mcxn947/board.c

@@ -291,8 +291,8 @@ void board_early_init_hook(void)
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
-	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
-	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 3U);
+	CLOCK_AttachClk(kPLL0_to_FLEXCAN0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))

boards/nxp/mcx_nx4x_evk/board.c

@@ -286,8 +286,8 @@ void board_early_init_hook(void)
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
-	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
-	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 3U);
+	CLOCK_AttachClk(kPLL0_to_FLEXCAN0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))