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drivers: pinctrl: Add support for RZ/G3S
This is the initial commit to support pinctrl driver for Renesas RZ/G3S Signed-off-by: Quang Le <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024 EPAM Systems
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>
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&pinctrl {
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/omit-if-no-ref/ scif0_pins: scif0 {
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scif0-pinmux {
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pinmux = <RZG_PINMUX(PORT_06, 3, 1)>, /* TXD */
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<RZG_PINMUX(PORT_06, 4, 1)>; /* RXD */
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};
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};
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/omit-if-no-ref/ scif1_pins: scif1 {
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scif1-pinmux {
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pinmux = <RZG_PINMUX(PORT_14, 0, 1)>, /* TXD */
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<RZG_PINMUX(PORT_14, 1, 1)>; /* RXD */
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};
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};
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/omit-if-no-ref/ scif3_pins: scif3 {
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scif3-pinmux {
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pinmux = <RZG_PINMUX(PORT_17, 3, 7)>, /* TXD */
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<RZG_PINMUX(PORT_17, 2, 7)>; /* RXD */
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};
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};
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/omit-if-no-ref/ scif5_pins: scif5 {
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scif5-pinmux {
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pinmux = <RZG_PINMUX(PORT_15, 1, 6)>, /* RXD */
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<RZG_PINMUX(PORT_15, 2, 6)>; /* TXD */
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};
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};
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};

‎drivers/pinctrl/renesas/CMakeLists.txt‎

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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c)
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add_subdirectory_ifdef(CONFIG_PINCTRL_RCAR_PFC rcar)

‎drivers/pinctrl/renesas/rz/Kconfig‎

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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RZT2M
@@ -7,3 +8,11 @@ config PINCTRL_RZT2M
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depends on DT_HAS_RENESAS_RZT2M_PINCTRL_ENABLED
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help
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Renesas RZ/T2M pinctrl driver
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config PINCTRL_RENESAS_RZ
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bool "Renesas RZ pin controller driver"
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default y
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depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED
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select USE_RZ_FSP_IOPORT
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help
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Enable Renesas RZ pinctrl driver.

‎drivers/pinctrl/renesas/rz/pinctrl_renesas_rz.c‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include "r_ioport.h"
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static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
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{
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uint32_t cfg = *(uint32_t *)&pin->config;
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R_IOPORT_PinCfg(NULL, pin->port_pin, cfg);
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_configure_pin(pins++);
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}
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return 0;
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}

‎dts/arm/renesas/rz/rzg/r9a08g045.dtsi‎

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};
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};
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};
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soc {
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pinctrl: pin-controller@41030000 {
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compatible = "renesas,rzg-pinctrl";
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reg = <0x41030000 DT_SIZE_K(64)>;
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reg-names = "pinctrl";
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};
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};
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};
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&nvic {

‎dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml‎

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# Copyright (c) 2024 Epam Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Below generic example shows of supported pinctrl definitions:
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
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example_pins: device_pin {
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device-pinmux {
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pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
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<RZG_PINMUX(PORT_08, 2, 5)>;
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bias_pull_up;
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renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
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drive-strength = <1>;
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};
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device-spins {
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pins = <BSP_IO_XSPI_IO0>, <BSP_IO_XSPI_IO4>;
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input-enable;
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renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
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drive-strength = <2>;
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};
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};
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compatible: renesas,rzg-pinctrl
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include: base.yaml
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properties:
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reg:
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required: true
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reg-names:
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required: true
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child-binding:
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description: |
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This RZG pins mux/cfg nodes description.
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child-binding:
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description: |
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The RZG pinmux/pincfg configuration nodes description.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-high-impedance
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- bias-pull-down
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- bias-pull-up
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- bias-pull-pin-default
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- drive-strength
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- input-enable
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- input-disable
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- output-enable
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- power-source
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- low-power-enable
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- low-power-disable
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properties:
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pinmux:
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type: array
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description: |
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Pinmux configuration node.
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Values are constructed from GPIO port number, pin number, and
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alternate function configuration number using the RZG_PINMUX()
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helper macro in pinctrl_rzg.h
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pins:
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type: array
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description: |
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Special Purpose pins configuration node.
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Values are define in pinctrl_rzg.h.
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Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
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drive-strength:
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type: int
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default: 0
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description: |
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Maximum sink or source current in mA for pin which shell be selected
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depending on device and pin group.
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renesas,filter:
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type: int
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default: 0
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description: |
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Digital Noise Filter configuration for a pin which shell be defined
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using RZG_FILTER_SET() helper macro in pinctrl_rzg.h to specify
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FILNUM_m and FILCLKSEL_m. With 24Mhz external clock:
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- min debounce time will be 166.666ns for FILNUM_m=0 and FILCLKSEL_m=0
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- max debounce time will be 24ms for FILNUM_m=3 and FILCLKSEL_m=3.
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This property intentionally redefined to avoid unnecessary conversation from usec to
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FILNUM_m and FILCLKSEL_m values depending on external clock value as this configuration
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is static.

‎include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
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/* Superset list of all possible IO ports. */
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#define PORT_00 0x0000 /* IO port 0 */
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#define PORT_01 0x1000 /* IO port 1 */
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#define PORT_02 0x1100 /* IO port 2 */
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#define PORT_03 0x1200 /* IO port 3 */
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#define PORT_04 0x1300 /* IO port 4 */
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#define PORT_05 0x0100 /* IO port 5 */
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#define PORT_06 0x0200 /* IO port 6 */
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#define PORT_07 0x1400 /* IO port 7 */
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#define PORT_08 0x1500 /* IO port 8 */
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#define PORT_09 0x1600 /* IO port 9 */
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#define PORT_10 0x1700 /* IO port 10 */
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#define PORT_11 0x0300 /* IO port 11 */
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#define PORT_12 0x0400 /* IO port 12 */
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#define PORT_13 0x0500 /* IO port 13 */
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#define PORT_14 0x0600 /* IO port 14 */
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#define PORT_15 0x0700 /* IO port 15 */
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#define PORT_16 0x0800 /* IO port 16 */
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#define PORT_17 0x0900 /* IO port 17 */
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#define PORT_18 0x0A00 /* IO port 18 */
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/*
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* Create the value contain port/pin/function information
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*
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* port: port number BSP_IO_PORT_00..BSP_IO_PORT_18
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* pin: pin number
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* func: pin function
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*/
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#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4))
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/* Special purpose port */
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#define BSP_IO_NMI 0xFFFF0000 /* NMI */
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#define BSP_IO_TMS_SWDIO 0xFFFF0100 /* TMS_SWDIO */
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#define BSP_IO_TDO 0xFFFF0101 /* TDO */
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#define BSP_IO_AUDIO_CLK1 0xFFFF0200 /* AUDIO_CLK1 */
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#define BSP_IO_AUDIO_CLK2 0xFFFF0201 /* AUDIO_CLK2 */
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#define BSP_IO_XSPI_SPCLK 0xFFFF0400 /* XSPI_SPCLK */
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#define BSP_IO_XSPI_RESET_N 0xFFFF0401 /* XSPI_RESET_N */
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#define BSP_IO_XSPI_WP_N 0xFFFF0402 /* XSPI_WP_N */
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#define BSP_IO_XSPI_DS 0xFFFF0403 /* XSPI_DS */
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#define BSP_IO_XSPI_CS0_N 0xFFFF0404 /* XSPI_CS0_N */
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#define BSP_IO_XSPI_CS1_N 0xFFFF0405 /* XSPI_CS1_N */
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#define BSP_IO_XSPI_IO0 0xFFFF0500 /* XSPI_IO0 */
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#define BSP_IO_XSPI_IO1 0xFFFF0501 /* XSPI_IO1 */
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#define BSP_IO_XSPI_IO2 0xFFFF0502 /* XSPI_IO2 */
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#define BSP_IO_XSPI_IO3 0xFFFF0503 /* XSPI_IO3 */
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#define BSP_IO_XSPI_IO4 0xFFFF0504 /* XSPI_IO4 */
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#define BSP_IO_XSPI_IO5 0xFFFF0505 /* XSPI_IO5 */
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#define BSP_IO_XSPI_IO6 0xFFFF0506 /* XSPI_IO6 */
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#define BSP_IO_XSPI_IO7 0xFFFF0507 /* XSPI_IO7 */
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#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */
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#define BSP_IO_I3C_SDA 0xFFFF0900 /* I3C_SDA */
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#define BSP_IO_I3C_SCL 0xFFFF0901 /* I3C_SCL */
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#define BSP_IO_SD0_CLK 0xFFFF1000 /* CD0_CLK */
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#define BSP_IO_SD0_CMD 0xFFFF1001 /* CD0_CMD */
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#define BSP_IO_SD0_RST_N 0xFFFF1002 /* CD0_RST_N */
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#define BSP_IO_SD0_DATA0 0xFFFF1100 /* SD0_DATA0 */
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#define BSP_IO_SD0_DATA1 0xFFFF1101 /* SD0_DATA1 */
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#define BSP_IO_SD0_DATA2 0xFFFF1102 /* SD0_DATA2 */
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#define BSP_IO_SD0_DATA3 0xFFFF1103 /* SD0_DATA3 */
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#define BSP_IO_SD0_DATA4 0xFFFF1104 /* SD0_DATA4 */
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#define BSP_IO_SD0_DATA5 0xFFFF1105 /* SD0_DATA5 */
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#define BSP_IO_SD0_DATA6 0xFFFF1106 /* SD0_DATA6 */
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#define BSP_IO_SD0_DATA7 0xFFFF1107 /* SD0_DATA7 */
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#define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */
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#define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */
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#define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */
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#define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */
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#define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */
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#define BSP_IO_SD1_DATA3 0xFFFF1303 /* SD1_DATA3 */
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/*FILNUM*/
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#define RZG_FILNUM_4_STAGE 0
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#define RZG_FILNUM_8_STAGE 1
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#define RZG_FILNUM_12_STAGE 2
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#define RZG_FILNUM_16_STAGE 3
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/*FILCLKSEL*/
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#define RZG_FILCLKSEL_NOT_DIV 0
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#define RZG_FILCLKSEL_DIV_9000 1
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#define RZG_FILCLKSEL_DIV_18000 2
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#define RZG_FILCLKSEL_DIV_36000 3
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#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
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#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/

‎modules/Kconfig.renesas_fsp‎

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Enable RA FSP Ethernet driver
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endif # HAS_RENESAS_RA_FSP
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if HAS_RENESAS_RZ_FSP
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config USE_RZ_FSP_IOPORT
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bool
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help
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Enable RZ FSP IOPORT driver
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endif

‎soc/renesas/rz/CMakeLists.txt‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories_ifdef(CONFIG_HAS_RENESAS_RZ_FSP common)
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add_subdirectory(${SOC_SERIES})

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