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boards: renesas: Add minimal support for board RZ/G3S-SMARC
This adds minimal support for board RZ/G3S-SMARC Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Tien Nguyen <[email protected]> Signed-off-by: Binh Nguyen <[email protected]>
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‎boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_RZG3S_SMARC
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select SOC_R9A08G045S33GBG

‎boards/renesas/rzg3s_smarc/board.cmake

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=R9A08G045S33_M33_0" "--speed=15000")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/renesas/rzg3s_smarc/board.yml

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board:
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name: rzg3s_smarc
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full_name: RZ/G3S SMARC Evaluation Board Kit
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vendor: renesas
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socs:
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- name: r9a08g045s33gbg

‎boards/renesas/rzg3s_smarc/doc/index.rst

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.. zephyr:board:: rzg3s_smarc
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Overview
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********
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The Renesas RZ/G3S SMARC Evaluation Board Kit (RZ/G3S-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
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* Device: RZ/G3S R9A08G045S33GBG
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* Cortex-A55 Single, Cortex-M33 x 2
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* BGA 359-pin, 14mmSq body, 0.5mm pitch
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* SMARC v2.1 Module Board Functions
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* LPDDR4 SDRAM: 1GB x 1pc
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* QSPI flash memory: 128Mb x 1pc
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* eMMC memory: 64GB x 1pc
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* PMIC power supply RAA215300A2GNP#HA3 implemented
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* microSD card x2
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* I3C connector
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* JTAG connector
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* ADC x8 channels
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* Current monitor (USB Micro B)
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* Carrier Board Functions
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* Gigabit Ethernet x2
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* USB2.0 x2ch (OTG x1ch, Host x1ch)
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* CAN-FD x2
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* microSD card x1
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* Mono speaker, Stereo headphone, Mic., and Aux..
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* PMOD x2
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* USB-Type C for power input
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* PCIe Gen2 4-lane slot (G3S supports only 1-lane)
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* M.2 Key E
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* M.2 Key B and SIM card
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* Coin cell battery holder (3.0V support)
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Hardware
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********
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The Renesas RZ/G3S MPU documentation can be found at `RZ/G3S Group Website`_
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.. figure:: rzg3s_block_diagram.webp
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:width: 600px
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:align: center
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:alt: RZ/G3S group feature
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RZ/G3S block diagram (Credit: Renesas Electronics Corporation)
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Supported Features
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==================
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The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core without FPU
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and the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | arch/arm |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | arch/arm |
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+-----------+------------+-------------------------------------+
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| PINCTRL | on-chip | pinctrl |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial |
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+-----------+------------+-------------------------------------+
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Other hardware features are currently not supported by the port.
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Programming and Debugging
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*************************
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RZ/G3S-EVKIT is designed to start different systems on different cores.
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It uses Yocto as the build system to build Linux system and boot loaders
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to run BL2 TF-A on Cortex-A55 System Core before starting Zephyr. The minimal steps are described below.
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1. Follow ''2.2 Building Images'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to prepare the build environment.
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2. Before build, add ``PLAT_M33_BOOT_SUPPORT=1`` to meta-renesas/meta-rzg3s/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend.
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.. code-block:: bash
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:emphasize-lines: 6
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require trusted-firmware-a.inc
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COMPATIBLE_MACHINE_rzg3s = "(rzg3s-dev|smarc-rzg3s)"
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PLATFORM_rzg3s-dev = "g3s"
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EXTRA_FLAGS_rzg3s-dev = "BOARD=dev14_1_lpddr PLAT_SYSTEM_SUSPEND=vbat"
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PLATFORM_smarc-rzg3s = "g3s"
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EXTRA_FLAGS_smarc-rzg3s = "BOARD=smarc PLAT_SYSTEM_SUSPEND=vbat PLAT_M33_BOOT_SUPPORT=1"
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3. Start the build:
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.. code-block:: bash
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MACHINE=smarc-rzg3s bitbake core-image-minimal
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The below necessary artifacts will be located in the build/tmp/deploy/images
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+---------------+-----------------------------+
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| Artifacts | File name |
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+===============+=============================+
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| Boot loader | bl2_bp_spi-smarc-rzg3s.srec |
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| | |
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| | fip-smarc-rzg3s.srec |
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+---------------+-----------------------------+
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| Flash Writer | FlashWriter-smarc-rzg3s.mot |
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+---------------+-----------------------------+
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4. Follow ''4.2 Startup Procedure'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ for power supply and board setting
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at SCIF download (SW_MODE[1:4] = OFF, ON, OFF, ON) and Cortex-A55 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, OFF)
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5. Follow ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to download Flash Writer to RAM
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6. Follow ''4.4 Write the Bootloader'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to write the boot loader
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to the target board by using Flash Writer.
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Applications for the ``rzg3s_smarc`` board can be built in the usual way as
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documented in :ref:`build_an_application`.
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Console
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=======
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The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART <https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/>`_
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to the upper side of ``PMOD1_3A``.
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Debugging
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=========
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It is possible to load and execute a Zephyr application binary on
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this board on the Cortex-M33 System Core from
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the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
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.. note::
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Currently it's required Renesas BL2 TF-A to be started on Cortex-A55 System Core
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before starting Zephyr as it configures clocks and the Cortex-M33 System Core before starting it.
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Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: rzg3s_smarc/r9a08g045s33gbg/cm33
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:goals: build debug
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Flashing
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========
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Zephyr application can be flashed to QSPI storage and then loaded by
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Renesas BL2 TF-A running on the Cortex-A55 System Core and starting binary on the Cortex-M33 System Core.
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The Zephyr application binary has to be converted to Motorolla S-record `SREC`_ format
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which is generated automatically in Zephyr application build directory with the extension ``s19``.
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.. _SREC: https://en.wikipedia.org/wiki/SREC_(file_format)
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.. _Flashing on QSPI:
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Flashing on QSPI using Flash Writer
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---------------------------------------
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Zephyr binary has to be converted to **srec** format.
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* Download and start **Flash Writer** as described in ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_
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* Use **XLS2** command to flash Zephyr binary
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* Input when asked:
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.. code-block:: console
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===== Please Input Program Top Address ============
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Please Input : H'23000
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===== Please Input Qspi Save Address ===
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Please Input : H'200000
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* Then send Zephyr **s19** file from terminal (use ''ascii'' mode)
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* Reboot the board in the **QSPI Boot Mode**
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.. code-block:: console
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-- Load Program to SRAM ---------------
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Flash writer for RZ/G3S Series V0.60 Jan.26,2023
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Product Code : RZ/G3S
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>XLS2
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===== Qspi writing of RZ/G2 Board Command =============
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Load Program to Spiflash
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Writes to any of SPI address.
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Program size & Qspi Save Address
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===== Please Input Program Top Address ============
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Please Input : H'23000
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===== Please Input Qspi Save Address ===
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Please Input : H'200000
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please send ! ('.' & CR stop load)
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I Flash memory...
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Erase Completed
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Write to SPI Flash memory.
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======= Qspi Save Information =================
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SpiFlashMemory Stat Address : H'00200000
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SpiFlashMemory End Address : H'002098E6
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===========================================================
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Flashing on QSPI using west
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---------------------------
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Before using ``flash`` command, the board must be set to Cortex-M33 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, ON).
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After flashing, it must be set back to Cortex-A55 cold boot to run.
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The minimal version of SEGGER JLink SW which can perform flashing of QSPI memory is v7.96.
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**Note:** It's verified that we can perform flashing successfully with SEGGER JLink SW v7.98g so please use this or later
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version.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: rzg3s_smarc/r9a08g045s33gbg/cm33
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:goals: build flash
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:compact:
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References
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**********
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.. target-notes::
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.. _RZ/G3S Group Website:
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https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
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.. _RZG3S-EVKIT Website:
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https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-evkit-evaluation-board-kit-rzg3s-mpu
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.. _SMARC EVK of RZ/G3S Linux Start-up Guide:
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https://www.renesas.com/us/en/document/gde/smarc-evk-rzg3s-linux-start-guide-rev104

‎boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp

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‎boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp

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‎boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts

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/*
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* Copyright (c) 2024 EPAM Systems
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <freq.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
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#include <arm/renesas/rz/rzg/r9a08g045.dtsi>
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#include "rzg3s_smarc-pinctrl.dtsi"
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/ {
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model = "Renesas RZ/G3S SMARC";
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compatible = "renesas,rzg3s-smarc";
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chosen {
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zephyr,sram = &sram_mcpu0;
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zephyr,flash = &spi_flash;
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zephyr,console = &scif1;
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zephyr,shell-uart = &scif1;
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};
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aliases {
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sw0 = &sw_1;
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sw1 = &sw_2;
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sw2 = &sw_3;
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};
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buttons {
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compatible = "gpio-keys";
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sw_1: button_1 {
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gpios = <&gpio18 0 GPIO_ACTIVE_LOW>;
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label = "SW1";
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zephyr,code = <INPUT_KEY_1>;
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};
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sw_2: button_2 {
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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label = "SW2";
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zephyr,code = <INPUT_KEY_2>;
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};
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sw_3: button_3 {
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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label = "SW3";
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zephyr,code = <INPUT_KEY_3>;
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};
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};
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ddr: memory@60000000 {
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compatible ="zephyr,memory-region", "mmio-sram";
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reg = <0x60000000 DT_SIZE_M(16)>;
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zephyr,memory-region = "DDR";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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sram_mcpu0: memory@23000 {
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compatible = "mmio-sram";
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reg = <0x23000 DT_SIZE_K(243)>;
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};
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/*
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* This node is defined to enable west flash support.
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* The base addr and size depends on ATF-F configuration, which is running on Cortex-A55 and
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* loading Zephyr app from xSPI flash.
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*/
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spi_flash: memory@80200000 {
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compatible = "mmio-sram";
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reg = <0x80200000 DT_SIZE_K(256)>;
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};
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};
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&scif1 {
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current-speed = <115200>;
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pinctrl-0 = <&scif1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gpio0{
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status = "okay";
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};
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&gpio18{
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status = "okay";
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};

‎boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml

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identifier: rzg3s_smarc/r9a08g045s33gbg/cm33
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name: Cortex-M33 for Renesas RZ/G3S SMARC
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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supported:
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- uart
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- gpio

‎boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig

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# Copyright (c) 2024 EPAM Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=ys
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CONFIG_UART_CONSOLE=y

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