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include/dt-bindings/clock: stm32: Factorize Clock source binding accessors
Rename and factorize clock source bindings accessors by moving them in common header file stm32_clock_control and remove them from include/dt-bindings/clock/stm32XY_clock.h files Signed-off-by: Erwan Gouriou <[email protected]>
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5 files changed

+126
-165
lines changed

5 files changed

+126
-165
lines changed

‎drivers/clock_control/clock_stm32_ll_h7.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -417,10 +417,10 @@ static inline int stm32_clock_control_configure(const struct device *dev,
417417

418418
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
419419

420-
dt_val = STM32H7_CLOCK_VAL_GET(pclken->enr) <<
421-
STM32H7_CLOCK_SHIFT_GET(pclken->enr);
420+
dt_val = STM32_CLOCK_VAL_GET(pclken->enr) <<
421+
STM32_CLOCK_SHIFT_GET(pclken->enr);
422422
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) +
423-
STM32H7_CLOCK_REG_GET(pclken->enr));
423+
STM32_CLOCK_REG_GET(pclken->enr));
424424
reg_val = *reg;
425425
reg_val &= ~dt_val;
426426
reg_val |= dt_val;

‎drivers/clock_control/clock_stm32_ll_u5.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -184,10 +184,10 @@ static inline int stm32_clock_control_configure(const struct device *dev,
184184
return err;
185185
}
186186

187-
dt_val = STM32U5_CLOCK_VAL_GET(pclken->enr) <<
188-
STM32U5_CLOCK_SHIFT_GET(pclken->enr);
187+
dt_val = STM32_CLOCK_VAL_GET(pclken->enr) <<
188+
STM32_CLOCK_SHIFT_GET(pclken->enr);
189189
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) +
190-
STM32U5_CLOCK_REG_GET(pclken->enr));
190+
STM32_CLOCK_REG_GET(pclken->enr));
191191
reg_val = *reg;
192192
reg_val |= dt_val;
193193
*reg = reg_val;

‎include/zephyr/drivers/clock_control/stm32_clock_control.h‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,4 +307,38 @@ struct stm32_pclken {
307307
#define STM32_DT_DEV_OPT_CLOCK_SUPPORT \
308308
(DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0)
309309

310+
/** Clock source binding accessors */
311+
312+
/**
313+
* @brief Obtain register field from clock configuration.
314+
*
315+
* @param clock clock bit field value.
316+
*/
317+
#define STM32_CLOCK_REG_GET(clock) \
318+
(((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
319+
320+
/**
321+
* @brief Obtain position field from clock configuration.
322+
*
323+
* @param clock Clock bit field value.
324+
*/
325+
#define STM32_CLOCK_SHIFT_GET(clock) \
326+
(((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
327+
328+
/**
329+
* @brief Obtain mask field from clock configuration.
330+
*
331+
* @param clock Clock bit field value.
332+
*/
333+
#define STM32_CLOCK_MASK_GET(clock) \
334+
(((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
335+
336+
/**
337+
* @brief Obtain value field from clock configuration.
338+
*
339+
* @param clock Clock bit field value.
340+
*/
341+
#define STM32_CLOCK_VAL_GET(clock) \
342+
(((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
343+
310344
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */

‎include/zephyr/dt-bindings/clock/stm32h7_clock.h‎

Lines changed: 42 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -74,55 +74,20 @@
7474
* @param val Clock value (0, 1, 2 or 3).
7575
*/
7676

77-
#define STM32H7_CLOCK_REG_MASK 0xFFU
78-
#define STM32H7_CLOCK_REG_SHIFT 0U
79-
#define STM32H7_CLOCK_SHIFT_MASK 0x1FU
80-
#define STM32H7_CLOCK_SHIFT_SHIFT 8U
81-
#define STM32H7_CLOCK_MASK_MASK 0x7U
82-
#define STM32H7_CLOCK_MASK_SHIFT 13U
83-
#define STM32H7_CLOCK_VAL_MASK 0x7U
84-
#define STM32H7_CLOCK_VAL_SHIFT 16U
85-
86-
#define STM32H7_CLOCK(val, mask, shift, reg) \
87-
((((reg) & STM32H7_CLOCK_REG_MASK) << STM32H7_CLOCK_REG_SHIFT) | \
88-
(((shift) & STM32H7_CLOCK_SHIFT_MASK) << STM32H7_CLOCK_SHIFT_SHIFT) | \
89-
(((mask) & STM32H7_CLOCK_MASK_MASK) << STM32H7_CLOCK_MASK_SHIFT) | \
90-
(((val) & STM32H7_CLOCK_VAL_MASK) << STM32H7_CLOCK_VAL_SHIFT))
91-
92-
93-
/* Accessors for clock value */
94-
95-
/**
96-
* @brief Obtain register field from clock configuration.
97-
*
98-
* @param clock clock bit field value.
99-
*/
100-
#define STM32H7_CLOCK_REG_GET(clock) \
101-
(((clock) >> STM32H7_CLOCK_REG_SHIFT) & STM32H7_CLOCK_REG_MASK)
102-
103-
/**
104-
* @brief Obtain position field from clock configuration.
105-
*
106-
* @param clock Clock bit field value.
107-
*/
108-
#define STM32H7_CLOCK_SHIFT_GET(clock) \
109-
(((clock) >> STM32H7_CLOCK_SHIFT_SHIFT) & STM32H7_CLOCK_SHIFT_MASK)
110-
111-
/**
112-
* @brief Obtain mask field from clock configuration.
113-
*
114-
* @param clock Clock bit field value.
115-
*/
116-
#define STM32H7_CLOCK_MASK_GET(clock) \
117-
(((clock) >> STM32H7_CLOCK_MASK_SHIFT) & STM32H7_CLOCK_MASK_MASK)
118-
119-
/**
120-
* @brief Obtain value field from clock configuration.
121-
*
122-
* @param clock Clock bit field value.
123-
*/
124-
#define STM32H7_CLOCK_VAL_GET(clock) \
125-
(((clock) >> STM32H7_CLOCK_VAL_SHIFT) & STM32H7_CLOCK_VAL_MASK)
77+
#define STM32_CLOCK_REG_MASK 0xFFU
78+
#define STM32_CLOCK_REG_SHIFT 0U
79+
#define STM32_CLOCK_SHIFT_MASK 0x1FU
80+
#define STM32_CLOCK_SHIFT_SHIFT 8U
81+
#define STM32_CLOCK_MASK_MASK 0x7U
82+
#define STM32_CLOCK_MASK_SHIFT 13U
83+
#define STM32_CLOCK_VAL_MASK 0x7U
84+
#define STM32_CLOCK_VAL_SHIFT 16U
85+
86+
#define STM32_CLOCK(val, mask, shift, reg) \
87+
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
88+
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
89+
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
90+
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
12691

12792
/** @brief RCC_DxCCIP register offset (RM0399.pdf) */
12893
#define D1CCIPR_REG 0x4C
@@ -132,39 +97,36 @@
13297

13398
/** @brief Device clk sources selection helpers (RM0399.pdf) */
13499
/** D1CCIPR devices */
135-
#define FMC_SEL(val) STM32H7_CLOCK(val, 3, 0, D1CCIPR_REG)
136-
#define QSPI_SEL(val) STM32H7_CLOCK(val, 3, 4, D1CCIPR_REG)
137-
#define DSI_SEL(val) STM32H7_CLOCK(val, 1, 8, D1CCIPR_REG)
138-
#define SDMMC_SEL(val) STM32H7_CLOCK(val, 1, 16, D1CCIPR_REG)
139-
#define CKPER_SEL(val) STM32H7_CLOCK(val, 3, 28, D1CCIPR_REG)
100+
#define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG)
101+
#define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
102+
#define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG)
103+
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG)
104+
#define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG)
140105
/** D2CCIP1R devices */
141-
#define SAI1_SEL(val) STM32H7_CLOCK(val, 7, 0, D2CCIP1R_REG)
142-
#define SAI23_SEL(val) STM32H7_CLOCK(val, 7, 6, D2CCIP1R_REG)
143-
#define SPI123_SEL(val) STM32H7_CLOCK(val, 7, 12, D2CCIP1R_REG)
144-
#define SPI45_SEL(val) STM32H7_CLOCK(val, 7, 16, D2CCIP1R_REG)
145-
#define SPDIF_SEL(val) STM32H7_CLOCK(val, 3, 20, D2CCIP1R_REG)
146-
#define DFSDM1_SEL(val) STM32H7_CLOCK(val, 1, 24, D2CCIP1R_REG)
147-
#define FDCAN_SEL(val) STM32H7_CLOCK(val, 3, 28, D2CCIP1R_REG)
148-
#define SWP_SEL(val) STM32H7_CLOCK(val, 1, 31, D2CCIP1R_REG)
106+
#define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG)
107+
#define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG)
108+
#define SPI123_SEL(val) STM32_CLOCK(val, 7, 12, D2CCIP1R_REG)
109+
#define SPI45_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIP1R_REG)
110+
#define SPDIF_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP1R_REG)
111+
#define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 24, D2CCIP1R_REG)
112+
#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 28, D2CCIP1R_REG)
113+
#define SWP_SEL(val) STM32_CLOCK(val, 1, 31, D2CCIP1R_REG)
149114
/** D2CCIP2R devices */
150-
#define USART2345678_SEL(val) STM32H7_CLOCK(val, 7, 0, D2CCIP2R_REG)
151-
#define USART16_SEL(val) STM32H7_CLOCK(val, 7, 3, D2CCIP2R_REG)
152-
#define RNG_SEL(val) STM32H7_CLOCK(val, 3, 8, D2CCIP2R_REG)
153-
#define I2C123_SEL(val) STM32H7_CLOCK(val, 3, 12, D2CCIP2R_REG)
154-
#define USB_SEL(val) STM32H7_CLOCK(val, 3, 20, D2CCIP2R_REG)
155-
#define CEC_SEL(val) STM32H7_CLOCK(val, 3, 22, D2CCIP2R_REG)
156-
#define LPTIM1_SEL(val) STM32H7_CLOCK(val, 7, 28, D2CCIP2R_REG)
115+
#define USART2345678_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP2R_REG)
116+
#define USART16_SEL(val) STM32_CLOCK(val, 7, 3, D2CCIP2R_REG)
117+
#define RNG_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIP2R_REG)
118+
#define I2C123_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIP2R_REG)
119+
#define USB_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP2R_REG)
120+
#define CEC_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIP2R_REG)
121+
#define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 28, D2CCIP2R_REG)
157122
/** D3CCIPR devices */
158-
#define LPUART1_SEL(val) STM32H7_CLOCK(val, 7, 0, D3CCIPR_REG)
159-
#define I2C4_SEL(val) STM32H7_CLOCK(val, 3, 8, D3CCIPR_REG)
160-
#define LPTIM2_SEL(val) STM32H7_CLOCK(val, 7, 10, D3CCIPR_REG)
161-
#define LPTIM345_SEL(val) STM32H7_CLOCK(val, 7, 13, D3CCIPR_REG)
162-
#define ADC_SEL(val) STM32H7_CLOCK(val, 3, 16, D3CCIPR_REG)
163-
#define SAI4A_SEL(val) STM32H7_CLOCK(val, 7, 21, D3CCIPR_REG)
164-
#define SAI4B_SEL(val) STM32H7_CLOCK(val, 7, 24, D3CCIPR_REG)
165-
#define SPI6_SEL(val) STM32H7_CLOCK(val, 7, 28, D3CCIPR_REG)
166-
167-
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
168-
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
123+
#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG)
124+
#define I2C4_SEL(val) STM32_CLOCK(val, 3, 8, D3CCIPR_REG)
125+
#define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 10, D3CCIPR_REG)
126+
#define LPTIM345_SEL(val) STM32_CLOCK(val, 7, 13, D3CCIPR_REG)
127+
#define ADC_SEL(val) STM32_CLOCK(val, 3, 16, D3CCIPR_REG)
128+
#define SAI4A_SEL(val) STM32_CLOCK(val, 7, 21, D3CCIPR_REG)
129+
#define SAI4B_SEL(val) STM32_CLOCK(val, 7, 24, D3CCIPR_REG)
130+
#define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG)
169131

170132
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32u5_clock.h‎

Lines changed: 44 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -64,55 +64,20 @@
6464
* @param val Clock value (0, 1, ... 7).
6565
*/
6666

67-
#define STM32U5_CLOCK_REG_MASK 0xFFU
68-
#define STM32U5_CLOCK_REG_SHIFT 0U
69-
#define STM32U5_CLOCK_SHIFT_MASK 0x1FU
70-
#define STM32U5_CLOCK_SHIFT_SHIFT 8U
71-
#define STM32U5_CLOCK_MASK_MASK 0x7U
72-
#define STM32U5_CLOCK_MASK_SHIFT 13U
73-
#define STM32U5_CLOCK_VAL_MASK 0x7U
74-
#define STM32U5_CLOCK_VAL_SHIFT 16U
75-
76-
#define STM32U5_CLOCK(val, mask, shift, reg) \
77-
((((reg) & STM32U5_CLOCK_REG_MASK) << STM32U5_CLOCK_REG_SHIFT) | \
78-
(((shift) & STM32U5_CLOCK_SHIFT_MASK) << STM32U5_CLOCK_SHIFT_SHIFT) | \
79-
(((mask) & STM32U5_CLOCK_MASK_MASK) << STM32U5_CLOCK_MASK_SHIFT) | \
80-
(((val) & STM32U5_CLOCK_VAL_MASK) << STM32U5_CLOCK_VAL_SHIFT))
81-
82-
83-
/* Accessors for clock value */
84-
85-
/**
86-
* @brief Obtain register field from clock configuration.
87-
*
88-
* @param clock clock bit field value.
89-
*/
90-
#define STM32U5_CLOCK_REG_GET(clock) \
91-
(((clock) >> STM32U5_CLOCK_REG_SHIFT) & STM32U5_CLOCK_REG_MASK)
92-
93-
/**
94-
* @brief Obtain position field from clock configuration.
95-
*
96-
* @param clock Clock bit field value.
97-
*/
98-
#define STM32U5_CLOCK_SHIFT_GET(clock) \
99-
(((clock) >> STM32U5_CLOCK_SHIFT_SHIFT) & STM32U5_CLOCK_SHIFT_MASK)
100-
101-
/**
102-
* @brief Obtain mask field from clock configuration.
103-
*
104-
* @param clock Clock bit field value.
105-
*/
106-
#define STM32U5_CLOCK_MASK_GET(clock) \
107-
(((clock) >> STM32U5_CLOCK_MASK_SHIFT) & STM32U5_CLOCK_MASK_MASK)
108-
109-
/**
110-
* @brief Obtain value field from clock configuration.
111-
*
112-
* @param clock Clock bit field value.
113-
*/
114-
#define STM32U5_CLOCK_VAL_GET(clock) \
115-
(((clock) >> STM32U5_CLOCK_VAL_SHIFT) & STM32U5_CLOCK_VAL_MASK)
67+
#define STM32_CLOCK_REG_MASK 0xFFU
68+
#define STM32_CLOCK_REG_SHIFT 0U
69+
#define STM32_CLOCK_SHIFT_MASK 0x1FU
70+
#define STM32_CLOCK_SHIFT_SHIFT 8U
71+
#define STM32_CLOCK_MASK_MASK 0x7U
72+
#define STM32_CLOCK_MASK_SHIFT 13U
73+
#define STM32_CLOCK_VAL_MASK 0x7U
74+
#define STM32_CLOCK_VAL_SHIFT 16U
75+
76+
#define STM32_CLOCK(val, mask, shift, reg) \
77+
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
78+
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
79+
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
80+
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
11681

11782
/** @brief RCC_CCIPRx register offset (RM0456.pdf) */
11883
#define CCIPR1_REG 0xE0
@@ -121,37 +86,37 @@
12186

12287
/** @brief Device clk sources selection helpers (RM0399.pdf) */
12388
/** CCIPR1 devices */
124-
#define USART1_SEL(val) STM32U5_CLOCK(val, 3, 0, CCIPR1_REG)
125-
#define USART2_SEL(val) STM32U5_CLOCK(val, 3, 2, CCIPR1_REG)
126-
#define USART3_SEL(val) STM32U5_CLOCK(val, 3, 4, CCIPR1_REG)
127-
#define USART4_SEL(val) STM32U5_CLOCK(val, 3, 6, CCIPR1_REG)
128-
#define USART5_SEL(val) STM32U5_CLOCK(val, 3, 8, CCIPR1_REG)
129-
#define I2C1_SEL(val) STM32U5_CLOCK(val, 3, 10, CCIPR1_REG)
130-
#define I2C2_SEL(val) STM32U5_CLOCK(val, 3, 12, CCIPR1_REG)
131-
#define I2C4_SEL(val) STM32U5_CLOCK(val, 3, 14, CCIPR1_REG)
132-
#define SPI2_SEL(val) STM32U5_CLOCK(val, 3, 16, CCIPR1_REG)
133-
#define LPTIM2_SEL(val) STM32U5_CLOCK(val, 3, 18, CCIPR1_REG)
134-
#define SPI1_SEL(val) STM32U5_CLOCK(val, 3, 20, CCIPR1_REG)
135-
#define SYSTICK_SEL(val) STM32U5_CLOCK(val, 3, 22, CCIPR1_REG)
136-
#define FDCAN1_SEL(val) STM32U5_CLOCK(val, 3, 24, CCIPR1_REG)
137-
#define ICKLK_SEL(val) STM32U5_CLOCK(val, 3, 26, CCIPR1_REG)
138-
#define TIMIC_SEL(val) STM32U5_CLOCK(val, 7, 29, CCIPR1_REG)
89+
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
90+
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
91+
#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG)
92+
#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG)
93+
#define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG)
94+
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG)
95+
#define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG)
96+
#define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG)
97+
#define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG)
98+
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG)
99+
#define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG)
100+
#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG)
101+
#define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG)
102+
#define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG)
103+
#define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG)
139104
/** CCIPR2 devices */
140-
#define MDF1_SEL(val) STM32U5_CLOCK(val, 7, 0, CCIPR2_REG)
141-
#define SAI1_SEL(val) STM32U5_CLOCK(val, 7, 5, CCIPR2_REG)
142-
#define SAI2_SEL(val) STM32U5_CLOCK(val, 7, 8, CCIPR2_REG)
143-
#define SAE_SEL(val) STM32U5_CLOCK(val, 1, 11, CCIPR2_REG)
144-
#define RNG_SEL(val) STM32U5_CLOCK(val, 3, 12, CCIPR2_REG)
145-
#define SDMMC_SEL(val) STM32U5_CLOCK(val, 1, 14, CCIPR2_REG)
146-
#define OCTOSPI_SEL(val) STM32U5_CLOCK(val, 3, 20, CCIPR2_REG)
105+
#define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG)
106+
#define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG)
107+
#define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG)
108+
#define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG)
109+
#define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
110+
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
111+
#define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
147112
/** CCIPR3 devices */
148-
#define LPUART1_SEL(val) STM32U5_CLOCK(val, 7, 0, CCIPR3_REG)
149-
#define SPI3_SEL(val) STM32U5_CLOCK(val, 3, 3, CCIPR3_REG)
150-
#define I2C3_SEL(val) STM32U5_CLOCK(val, 3, 6, CCIPR3_REG)
151-
#define LPTIM34_SEL(val) STM32U5_CLOCK(val, 3, 8, CCIPR3_REG)
152-
#define LPTIM1_SEL(val) STM32U5_CLOCK(val, 3, 10, CCIPR3_REG)
153-
#define ADCDAC_SEL(val) STM32U5_CLOCK(val, 7, 12, CCIPR3_REG)
154-
#define DAC1_SEL(val) STM32U5_CLOCK(val, 1, 15, CCIPR3_REG)
155-
#define ADF1_SEL(val) STM32U5_CLOCK(val, 7, 16, CCIPR3_REG)
156113

157114
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
115+
#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG)
116+
#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG)
117+
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG)
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#define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG)
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#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG)
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#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG)
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#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG)
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#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG)

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