@@ -86,9 +86,9 @@ extern "C" {
8686#define RCC_OFFSET_LPTIM23CKSELR 0x870UL
8787#define RCC_OFFSET_LPTIM1CKSELR 0x874UL
8888
89- #define CONFIG_SHIFT 0U
90- #define MASK_SHIFT 8U
91- #define REG_SHIFT 16U
89+ #define RCC_CONFIG_SHIFT 0U
90+ #define RCC_MASK_SHIFT 8U
91+ #define RCC_REG_SHIFT 16U
9292
9393
9494/* Define all reset flags mask */
@@ -110,18 +110,18 @@ extern "C" {
110110 --------------------------------------------------------*/
111111
112112#define LL_CLKSOURCE_MASK (__CLKSOURCE__ ) \
113- (((__CLKSOURCE__) >> MASK_SHIFT ) & 0xFFUL)
113+ (((__CLKSOURCE__) >> RCC_MASK_SHIFT ) & 0xFFUL)
114114
115115#define LL_CLKSOURCE_CONFIG (__CLKSOURCE__ ) \
116- (((__CLKSOURCE__) >> CONFIG_SHIFT ) & 0xFFUL)
116+ (((__CLKSOURCE__) >> RCC_CONFIG_SHIFT ) & 0xFFUL)
117117
118118#define LL_CLKSOURCE_REG (__CLKSOURCE__ ) \
119- (((__CLKSOURCE__) >> REG_SHIFT ) & 0xFFFUL)
119+ (((__CLKSOURCE__) >> RCC_REG_SHIFT ) & 0xFFFUL)
120120
121121#define LL_CLKSOURCE (__REG__ , __MSK__ , __CLK__ ) \
122- ((uint32_t)((((__REG__) ) << REG_SHIFT ) | \
123- (( __MSK__ ) << MASK_SHIFT ) | \
124- (( __CLK__ ) << CONFIG_SHIFT )))
122+ ((uint32_t)((((__REG__) ) << RCC_REG_SHIFT ) | \
123+ (( __MSK__ ) << RCC_MASK_SHIFT ) | \
124+ (( __CLK__ ) << RCC_CONFIG_SHIFT )))
125125
126126/**
127127 * @}
@@ -3031,7 +3031,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
30313031{
30323032 __IO const uint32_t * pReg = (uint32_t * )((uint32_t )((uint32_t )(& RCC -> I2C46CKSELR ) + LL_CLKSOURCE_REG (Periph )));
30333033
3034- return (uint32_t )(Periph | ((READ_BIT (* pReg , LL_CLKSOURCE_MASK (Periph ))) << CONFIG_SHIFT ));
3034+ return (uint32_t )(Periph | ((READ_BIT (* pReg , LL_CLKSOURCE_MASK (Periph ))) << RCC_CONFIG_SHIFT ));
30353035}
30363036
30373037/**
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