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board: nrf: Add nRF54LM20DK board
Adding board for nRF54LM20A device. Signed-off-by: Karol Lasończyk <[email protected]>
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‎boards/nordic/nrf54lm20dk/Kconfig.defconfig‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP

‎boards/nordic/nrf54lm20dk/Kconfig.nrf54lm20dk‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF54LM20DK
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select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
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select SOC_NRF54LM20A_ENGA_CPUFLPR if BOARD_NRF54LM20DK_NRF54LM20A_CPUFLPR

‎boards/nordic/nrf54lm20dk/board.cmake‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP)
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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elseif(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR)
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board_runner_args(jlink "--speed=4000")
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endif()
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nordic/nrf54lm20dk/board.yml‎

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board:
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name: nrf54lm20dk
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full_name: nRF54LM20 DK
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vendor: nordic
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socs:
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- name: nrf54lm20a
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variants:
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- name: xip
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cpucluster: cpuflpr
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runners:
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run_once:
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'--recover':
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- runners:
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- nrfjprog
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- nrfutil
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run: first
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
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'--erase':
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- runners:
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- nrfjprog
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- jlink
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- nrfutil
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run: first
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
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'--reset':
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- runners:
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- nrfjprog
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- jlink
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- nrfutil
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run: last
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip

‎boards/nordic/nrf54lm20dk/doc/index.rst‎

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.. zephyr:board:: nrf54lm20dk
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Overview
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********
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The nRF54LM20 Development Kit hardware provides support for the Nordic Semiconductor
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nRF54LM20A Arm Cortex-M33 CPU and the following devices:
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* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
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* CLOCK
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* RRAM
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* :abbr:`GPIO (General Purpose Input Output)`
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* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
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* MEMCONF
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* :abbr:`MPU (Memory Protection Unit)`
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* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
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* :abbr:`PWM (Pulse Width Modulation)`
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* :abbr:`GRTC (Global real-time counter)`
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* Segger RTT (RTT Console)
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* :abbr:`SPI (Serial Peripheral Interface)`
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* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
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* :abbr:`WDT (Watchdog Timer)`
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Hardware
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********
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nRF54LM20 DK has two crystal oscillators:
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* High-frequency 32 MHz crystal oscillator (HFXO)
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* Low-frequency 32.768 kHz crystal oscillator (LFXO)
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The crystal oscillators can be configured to use either
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internal or external capacitors.
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Applications for the ``nrf54lm20dk/nrf54lm20a/cpuapp`` board target can be
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built, flashed, and debugged in the usual way. See
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:ref:`build_an_application` and :ref:`application_run` for more details on
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building and running.
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Applications for the ``nrf54lm20dk/nrf54lm20a/cpuflpr`` board target need
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to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
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Enter the following command to compile ``hello_world`` for the FLPR core:
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.. code-block:: console
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west build -p -b nrf54lm20dk/nrf54lm20a/cpuflpr --sysbuild
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Flashing
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========
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As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
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application.
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.. warning::
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When programming the device, you might get an error similar to the following message::
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ERROR: The operation attempted is unavailable due to readback protection in
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ERROR: your device. Please use --recover to unlock the device.
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This error occurs when readback protection is enabled.
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To disable the readback protection, you must *recover* your device.
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Enter the following command to recover the core::
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west flash --recover
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The ``--recover`` command erases the flash memory and then writes a small binary into
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the recovered flash memory.
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This binary prevents the readback protection from enabling itself again after a pin
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reset or power cycle.
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Follow the instructions in the :ref:`nordic_segger` page to install
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and configure all the necessary software. Further information can be
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found in :ref:`nordic_segger_flashing`.
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To build and program the sample to the nRF54LM20 DK, complete the following steps:
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First, connect the nRF54LM20 DK to you computer using the IMCU USB port on the DK.
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Next, build the sample by running the following command:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: nrf54lm20dk/nrf54lm20a/cpuapp
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:goals: build flash
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Testing the LEDs and buttons in the nRF54LM20 DK
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************************************************
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Test the nRF54LM20 DK with a :zephyr:code-sample:`blinky` sample.

‎boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is common to the secure and non-secure domain */
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#include <nordic/nrf54lm20a_enga_cpuapp.dtsi>
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#include "nrf54lm20dk_nrf54lm20a-common.dtsi"
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/ {
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chosen {
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zephyr,console = &uart20;
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zephyr,shell-uart = &uart20;
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zephyr,uart-mcumgr = &uart20;
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zephyr,bt-mon-uart = &uart20;
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zephyr,bt-c2h-uart = &uart20;
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zephyr,flash-controller = &rram_controller;
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zephyr,flash = &cpuapp_rram;
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zephyr,bt-hci = &bt_hci_sdc;
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zephyr,ieee802154 = &ieee802154;
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};
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};
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&cpuapp_sram {
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status = "okay";
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};
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&hfpll {
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clock-frequency = <DT_FREQ_M(128)>;
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <17000>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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};
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&vregmain {
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status = "okay";
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regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
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};
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&grtc {
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
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child-owned-channels = <3 4 7 8 9 10 11>;
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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(449)>;
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};
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slot0_ns_partition: partition@80400 {
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label = "image-0-nonsecure";
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reg = <0x80400 DT_SIZE_K(449)>;
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};
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slot1_partition: partition@f0800 {
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label = "image-1";
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reg = <0xf0800 DT_SIZE_K(449)>;
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};
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slot1_ns_partition: partition@160c00 {
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label = "image-1-nonsecure";
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reg = <0x160c00 DT_SIZE_K(449)>;
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};
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storage_partition: partition@1d1000 {
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label = "storage";
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reg = <0x1d1000 DT_SIZE_K(36)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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};
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&nfct {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&radio {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};
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&bt_hci_controller {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};
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zephyr_udc0: &usbhs {
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status = "okay";
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};
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&spi00 {
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status = "okay";
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cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&spi00_default>;
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pinctrl-1 = <&spi00_sleep>;
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pinctrl-names = "default", "sleep";
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mx25r64: mx25r6435f@0 {
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compatible = "jedec,spi-nor";
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status = "disabled";
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reg = <0>;
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spi-max-frequency = <8000000>;
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jedec-id = [c2 28 17];
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sfdp-bfp = [
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e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
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ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
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10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
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30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
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];
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size = <67108864>;
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has-dpd;
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t-enter-dpd = <10000>;
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t-exit-dpd = <35000>;
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};
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};

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