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dts: renesas: Add Clock Control support for RZ/A3UL, V2L
Add Clock Control nodes to Renesas RZ/A3UL, V2L devicetree Signed-off-by: Quang Le <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
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‎dts/arm/renesas/rz/rzv/r9a07g054.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
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#include <mem.h>
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#include <freq.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/renesas_rzv_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
@@ -33,6 +34,12 @@
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};
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};
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osc: osc {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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};
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3643
soc {
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adc: adc@40059000 {
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compatible = "renesas,rz-adc-c";
@@ -45,6 +52,133 @@
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status = "disabled";
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};
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cpg: clock-controller@41010000 {
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compatible = "renesas,rz-cpg";
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reg = <0x41010000 DT_SIZE_K(64)>;
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#clock-cells = <1>;
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status = "okay";
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iclk: iclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(1200)>;
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#clock-cells = <0>;
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};
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i2clk: i2clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(200)>;
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#clock-cells = <0>;
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};
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gclk: gclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(500)>;
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#clock-cells = <0>;
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};
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s0clk: s0clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(12)>;
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#clock-cells = <0>;
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};
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spi0clk: spi0clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(200)>;
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#clock-cells = <0>;
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};
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spi1clk: spi1clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(100)>;
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#clock-cells = <0>;
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};
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sd0clk: sd0clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(533)>;
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#clock-cells = <0>;
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};
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sd1clk: sd1clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(533)>;
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#clock-cells = <0>;
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};
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m0clk: m0clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(200)>;
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#clock-cells = <0>;
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};
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m1clk: m1clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(3000)>;
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#clock-cells = <0>;
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};
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m2clk: m2clk {
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compatible = "fixed-clock";
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clock-frequency = <266500000>;
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#clock-cells = <0>;
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};
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m3clk: m3clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(3000)>;
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#clock-cells = <0>;
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};
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m4clk: m4clk {
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compatible = "fixed-clock";
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clock-frequency = <16656000>;
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#clock-cells = <0>;
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};
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hpclk: hpclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(250)>;
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#clock-cells = <0>;
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};
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tsuclk: tsuclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(80)>;
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#clock-cells = <0>;
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};
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ztclk: ztclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(100)>;
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#clock-cells = <0>;
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};
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p0clk: p0clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(100)>;
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#clock-cells = <0>;
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};
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p1clk: p1clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(200)>;
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#clock-cells = <0>;
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};
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p2clk: p2clk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(100)>;
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#clock-cells = <0>;
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};
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atclk: atclk {
176+
compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(400)>;
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#clock-cells = <0>;
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};
180+
};
181+
48182
pinctrl: pin-controller@41030000 {
49183
compatible = "renesas,rzv-pinctrl";
50184
reg = <0x41030000 DT_SIZE_K(64)>;

‎dts/arm64/renesas/rz/rza/r9a07g063.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <zephyr/dt-bindings/gpio/gpio.h>
1212
#include <zephyr/dt-bindings/pwm/renesas_rz_pwm.h>
1313
#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/renesas_rza_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
@@ -39,9 +40,216 @@
3940
interrupt-parent = <&gic>;
4041
};
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osc: osc {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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};
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4249
soc {
4350
interrupt-parent = <&gic>;
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cpg: clock-controller@11010000 {
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compatible = "renesas,rz-cpg";
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reg = <0x11010000 DT_SIZE_K(64)>;
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clocks = <&osc>;
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#clock-cells = <1>;
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status = "okay";
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59+
pll1: pll1 {
60+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(1000)>;
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#clock-cells = <1>;
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};
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pll2_1600: pll2-1600 {
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compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(1600)>;
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#clock-cells = <1>;
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};
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pll2_533: pll2-533 {
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compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(533)>;
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#clock-cells = <1>;
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};
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pll3_1600: pll3-1600 {
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compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(1600)>;
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#clock-cells = <1>;
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};
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pll3_533: pll3-533 {
84+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(533)>;
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#clock-cells = <1>;
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};
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pll3_400: pll3-400 {
90+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(400)>;
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#clock-cells = <1>;
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};
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pll4: pll4 {
96+
compatible = "renesas,rz-cpg-pll";
97+
clock-frequency = <DT_FREQ_M(1600)>;
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#clock-cells = <1>;
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};
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pll5_1500: pll5-1500 {
102+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(1500)>;
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#clock-cells = <1>;
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};
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pll5_500: pll5-500 {
108+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(500)>;
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#clock-cells = <1>;
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};
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pll6: pll6 {
114+
compatible = "renesas,rz-cpg-pll";
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clock-frequency = <DT_FREQ_M(500)>;
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#clock-cells = <1>;
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};
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iclk: iclk {
120+
compatible = "renesas,rz-cpg-clock";
121+
clocks = <&pll1 1>;
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div = <1>;
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#clock-cells = <0>;
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};
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sd0clk: sd0clk {
127+
compatible = "renesas,rz-cpg-clock";
128+
clocks = <&pll2_533 2>;
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div = <1>;
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#clock-cells = <0>;
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};
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sd1clk: sd1clk {
134+
compatible = "renesas,rz-cpg-clock";
135+
clocks = <&pll2_1600 4>;
136+
div = <1>;
137+
#clock-cells = <0>;
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};
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140+
p0clk: p0clk {
141+
compatible = "renesas,rz-cpg-clock";
142+
clocks = <&pll2_1600 16>;
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div = <1>;
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#clock-cells = <0>;
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};
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147+
tsuclk: tsuclk {
148+
compatible = "renesas,rz-cpg-clock";
149+
clocks = <&pll2_1600 20>;
150+
div = <1>;
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#clock-cells = <0>;
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};
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atclk: atclk {
155+
compatible = "renesas,rz-cpg-clock";
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clocks = <&pll3_1600 4>;
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div = <1>;
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#clock-cells = <0>;
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};
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i2clk: i2clk {
162+
compatible = "renesas,rz-cpg-clock";
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clocks = <&pll3_1600 8>;
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div = <1>;
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#clock-cells = <0>;
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};
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p1clk: p1clk {
169+
compatible = "renesas,rz-cpg-clock";
170+
clocks = <&pll3_1600 8>;
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div = <1>;
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#clock-cells = <0>;
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};
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175+
m0clk: m0clk {
176+
compatible = "renesas,rz-cpg-clock";
177+
clocks = <&pll3_1600 8>;
178+
div = <1>;
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#clock-cells = <0>;
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};
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182+
ztclk: ztclk {
183+
compatible = "renesas,rz-cpg-clock";
184+
clocks = <&pll3_1600 16>;
185+
div = <1>;
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#clock-cells = <0>;
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};
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p2clk: p2clk {
190+
compatible = "renesas,rz-cpg-clock";
191+
clocks = <&pll3_1600 16>;
192+
div = <1>;
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#clock-cells = <0>;
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};
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spi0clk: spi0clk {
197+
compatible = "renesas,rz-cpg-clock";
198+
clocks = <&pll3_533 2>;
199+
div = <2>;
200+
#clock-cells = <0>;
201+
};
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spi1clk: spi1clk {
204+
compatible = "renesas,rz-cpg-clock";
205+
clocks = <&pll3_533 4>;
206+
div = <2>;
207+
#clock-cells = <0>;
208+
};
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210+
m2clk: m2clk {
211+
compatible = "renesas,rz-cpg-clock";
212+
clocks = <&pll3_533 2>;
213+
div = <1>;
214+
#clock-cells = <0>;
215+
};
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217+
oc0clk: oc0clk {
218+
compatible = "renesas,rz-cpg-clock";
219+
clocks = <&pll3_400 2>;
220+
div = <1>;
221+
#clock-cells = <0>;
222+
};
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224+
oc1clk: oc1clk {
225+
compatible = "renesas,rz-cpg-clock";
226+
clocks = <&pll3_400 4>;
227+
div = <1>;
228+
#clock-cells = <0>;
229+
};
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231+
s0clk: s0clk {
232+
compatible = "renesas,rz-cpg-clock";
233+
clocks = <&pll4 2>;
234+
div = <1>;
235+
#clock-cells = <0>;
236+
};
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238+
m3clk: m3clk {
239+
compatible = "renesas,rz-cpg-clock";
240+
clocks = <&pll5_1500 1>;
241+
div = <2>;
242+
#clock-cells = <0>;
243+
};
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245+
hpclk: hpclk {
246+
compatible = "renesas,rz-cpg-clock";
247+
clocks = <&pll6 2>;
248+
div = <1>;
249+
#clock-cells = <0>;
250+
};
251+
};
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45253
gic: interrupt-controller@11900000 {
46254
compatible = "arm,gic-v3", "arm,gic";
47255
reg = <0x11900000 0x10000>, /* GICD */

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