arch: riscv: use CONFIG_RISCV_MCAUSE_EXCEPTION_MASK

gmarull · carlescufi · commit 452a2f67cdac · 2024-01-15T09:58:03.000+01:00
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).

Signed-off-by: Gerard Marull-Paretas &lt;gerard@teslabs.com&gt;
diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c
@@ -168,7 +168,7 @@ void _Fault(z_arch_esf_t *esf)
 	__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
 #endif
 
-	mcause &= SOC_MCAUSE_EXP_MASK;
+	mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
 	LOG_ERR("");
 	LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
 #ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
diff --git a/arch/riscv/core/irq_manage.c b/arch/riscv/core/irq_manage.c
@@ -20,7 +20,7 @@ FUNC_NORETURN void z_irq_spurious(const void *unused)
 
 	mcause = csr_read(mcause);
 
-	mcause &= SOC_MCAUSE_EXP_MASK;
+	mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
 
 	LOG_ERR("Spurious interrupt detected! IRQ: %ld", mcause);
 #if defined(CONFIG_RISCV_HAS_PLIC)
diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S
@@ -295,7 +295,7 @@ no_fp:	/* increment _current->arch.exception_depth */
 	 * to report the exception.
 	 */
 	csrr t0, mcause
-	li t2, SOC_MCAUSE_EXP_MASK
+	li t2, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
 	and t0, t0, t2
 
 	/*
@@ -528,7 +528,7 @@ on_irq_stack:
 
 	/* Get IRQ causing interrupt */
 	csrr a0, mcause
-	li t0, SOC_MCAUSE_EXP_MASK
+	li t0, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
 	and a0, a0, t0
 
 	/*
diff --git a/include/zephyr/arch/riscv/irq.h b/include/zephyr/arch/riscv/irq.h
@@ -91,7 +91,7 @@ static inline void arch_isr_direct_footer(int swap)
 
 	/* Get the IRQ number */
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
-	mcause &= SOC_MCAUSE_EXP_MASK;
+	mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
 
 	/* Clear the pending IRQ */
 	__soc_handle_irq(mcause);
diff --git a/soc/riscv/common/riscv-privileged/soc_common.h b/soc/riscv/common/riscv-privileged/soc_common.h
@@ -16,9 +16,6 @@
 #define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
 #define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
 
-/* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK          CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
-
 #ifndef _ASMLANGUAGE
 
 #include <zephyr/drivers/interrupt_controller/riscv_clic.h>
diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.h b/soc/riscv/espressif_esp32/esp32c3/soc.h
@@ -21,9 +21,6 @@
 #define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
 #define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
 
-/* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
-
 #ifndef _ASMLANGUAGE
 
 void __esp_platform_start(void);
diff --git a/soc/riscv/ite_ec/common/soc_common.h b/soc/riscv/ite_ec/common/soc_common.h
@@ -14,11 +14,6 @@
 
 #include "chip_chipregs.h"
 
-/* SOC-specific MCAUSE bitfields */
-
-/* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
-
 #ifndef _ASMLANGUAGE
 
 #ifdef CONFIG_HAS_ITE_INTC
diff --git a/soc/riscv/openisa_rv32m1/Kconfig.defconfig b/soc/riscv/openisa_rv32m1/Kconfig.defconfig
@@ -33,6 +33,9 @@ config RISCV_SOC_OFFSETS
 config RISCV_SOC_INTERRUPT_INIT
 	default y
 
+config RISCV_MCAUSE_EXCEPTION_MASK
+	default 0x1F
+
 # We need to disable the watchdog out of reset, as it's enabled by
 # default. Use the WDOG_INIT hook for doing that.
 config WDOG_INIT
diff --git a/soc/riscv/openisa_rv32m1/soc_ri5cy.h b/soc/riscv/openisa_rv32m1/soc_ri5cy.h
@@ -40,19 +40,4 @@
 #define RI5CY_PRIVLV    0xC10
 #define RI5CY_MHARTID   0xF14
 
-/*
- * Map from SoC-specific configuration to generic Zephyr macros.
- *
- * These are expected by the code in arch/, and must be provided for
- * the kernel to work (or even build at all).
- *
- * Some of these may also apply to ZERO-RISCY; needs investigation.
- */
-
-/*
- * Exception code mask. Use of the bottom five bits is a subset of
- * what the standard allocates (which is XLEN-1 bits).
- */
-#define SOC_MCAUSE_EXP_MASK 0x1F
-
 #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ */
diff --git a/soc/riscv/openisa_rv32m1/soc_zero_riscy.h b/soc/riscv/openisa_rv32m1/soc_zero_riscy.h
@@ -28,19 +28,4 @@
 #define ZERO_RISCY_PCMR    0x7A1U
 #define ZERO_RISCY_MHARTID 0xF14U
 
-/*
- * Map from SoC-specific configuration to generic Zephyr macros.
- *
- * These are expected by the code in arch/, and must be provided for
- * the kernel to work (or even build at all).
- *
- * Some of these may also apply to ZERO-RISCY; needs investigation.
- */
-
-/*
- * Exception code mask. Use of the bottom five bits is a subset of
- * what the standard allocates (which is XLEN-1 bits).
- */
-#define SOC_MCAUSE_EXP_MASK 0x1F
-
 #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ */
