arch: riscv: remove SOC from RISCV_SOC_MCAUSE_EXCEPTION_MASK

gmarull · carlescufi · commit ee6097795855 · 2024-01-15T09:58:03.000+01:00
Just to stay consistent with other RISC-V related settings.

Signed-off-by: Gerard Marull-Paretas &lt;gerard@teslabs.com&gt;
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
@@ -159,7 +159,7 @@ config RISCV_SOC_INTERRUPT_INIT
 	  Enable SOC-based interrupt initialization
 	  (call soc_interrupt_init, within _IntLibInit when enabled)
 
-config RISCV_SOC_MCAUSE_EXCEPTION_MASK
+config RISCV_MCAUSE_EXCEPTION_MASK
 	hex
 	default 0x7FFFFFFFFFFFFFFF if 64BIT
 	default 0x7FFFFFFF
diff --git a/soc/riscv/common/riscv-privileged/soc_common.h b/soc/riscv/common/riscv-privileged/soc_common.h
@@ -17,7 +17,7 @@
 #define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
 
 /* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK          CONFIG_RISCV_SOC_MCAUSE_EXCEPTION_MASK
+#define SOC_MCAUSE_EXP_MASK          CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
 
 #ifndef _ASMLANGUAGE
 
diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103
@@ -14,7 +14,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	# The CPU frequency is set to the maximum value of 108MHz by default.
 	default 27000000
 
-config RISCV_SOC_MCAUSE_EXCEPTION_MASK
+config RISCV_MCAUSE_EXCEPTION_MASK
 	default 0xFFF
 
 config RISCV_SOC_INTERRUPT_INIT
